From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40MhVz1L9WzDqRk for ; Fri, 13 Apr 2018 12:27:07 +1000 (AEST) Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id 40MhVz0jVcz8tT4 for ; Fri, 13 Apr 2018 12:27:07 +1000 (AEST) Received: from mail-pl0-x232.google.com (mail-pl0-x232.google.com [IPv6:2607:f8b0:400e:c01::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40MhVy454Vz9s0x for ; Fri, 13 Apr 2018 12:27:06 +1000 (AEST) Received: by mail-pl0-x232.google.com with SMTP id v5-v6so5189096plo.4 for ; Thu, 12 Apr 2018 19:27:06 -0700 (PDT) Date: Fri, 13 Apr 2018 12:26:54 +1000 From: Nicholas Piggin To: Michael Ellerman Cc: linuxppc-dev@ozlabs.org Subject: Re: [PATCH] powerpc/64s: Fix CPU_FTRS_ALWAYS vs DT CPU features Message-ID: <20180413122654.7e38689d@roar.ozlabs.ibm.com> In-Reply-To: <20180412134751.25098-1-mpe@ellerman.id.au> References: <20180412134751.25098-1-mpe@ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Thu, 12 Apr 2018 23:47:51 +1000 Michael Ellerman wrote: > The cpu_has_feature() mechanism has an optimisation where at build > time we construct a mask of the CPU feature bits that will always be > true for the given .config, based on the platform/bitness/etc. that we > are building for. > > That is incompatible with DT CPU features, where the set of CPU > features is dependent on feature flags that are given to us by > firmware. > > The result is that some feature bits can not be *disabled* by DT CPU > features. Or more accurately, they can be disabled but they will still > appear in the ALWAYS mask, meaning cpu_has_feature() will always > return true for them. > > In the past this hasn't really been a problem because on Book3S > 64 (where we support DT CPU features), the set of ALWAYS bits has been > very small. That was because we always built for POWER4 and later, > meaning the set of common bits was small. > > The only bit that could be cleared by DT CPU features that was also in > the ALWAYS mask was CPU_FTR_NODSISRALIGN, and that was only used in > the alignment handler to create a fake DSISR. That code was itself > deleted in 31bfdb036f12 ("powerpc: Use instruction emulation > infrastructure to handle alignment faults") (Sep 2017). > > However the set of ALWAYS features changed with the recent commit > db5ae1c155af ("powerpc/64s: Refine feature sets for little endian > builds") which restricted the set of feature flags when building > little endian to Power7 or later. That caused the ALWAYS mask to > become much larger for little endian builds. > > The result is that the following feature bits can currently not > be *disabled* by DT CPU features: > > CPU_FTR_REAL_LE, CPU_FTR_MMCRA, CPU_FTR_CTRL, CPU_FTR_SMT, > CPU_FTR_PURR, CPU_FTR_SPURR, CPU_FTR_DSCR, CPU_FTR_PKEY, > CPU_FTR_VMX_COPY, CPU_FTR_CFAR, CPU_FTR_HAS_PPR. > > To fix it we need to mask the set of ALWAYS features with the base set > of DT CPU features, ie. the features that are always enabled by DT CPU > features. That way there are no bits in the ALWAYS mask that are not > also always set by DT CPU features. > > Fixes: db5ae1c155af ("powerpc/64s: Refine feature sets for little endian builds") > Signed-off-by: Michael Ellerman Looks good to me. Reviewed-by: Nicholas Piggin