From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mx2.suse.de ([195.135.220.15]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_CAMELLIA_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1f8WJr-0005cW-KZ for speck@linutronix.de; Tue, 17 Apr 2018 21:31:11 +0200 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 60585AF95 for ; Tue, 17 Apr 2018 19:31:06 +0000 (UTC) Date: Tue, 17 Apr 2018 21:31:05 +0200 From: Borislav Petkov Subject: [MODERATED] Re: GPZv4 Message-ID: <20180417193105.GD3890@pd.tnic> References: MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Tue, Apr 17, 2018 at 02:26:58PM -0400, speck for Jon Masters wrote: > * AMD - They have chicken bits that can disable SSB. They won't provide > these except on the condition that we agree not to disable by default. > Therefore, I have the magic bit info but can't share it quite yet. It Oh, we know the bits. > involves writing into two uarch specific MSRs and won't be SPEC_CTRL. I > can assist coordinating whatever is agreed here getting back to AMD. There's nothing to coordinate - the default setting should be off on AMD, that's it. --=20 Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imend=C3=B6rffer, Jane Smithard, Graham Norton, HR= B 21284 (AG N=C3=BCrnberg) --=20