From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com ([134.134.136.24]:2996 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753201AbeDSPvo (ORCPT ); Thu, 19 Apr 2018 11:51:44 -0400 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Lucas De Marchi , Rodrigo Vivi , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Daniel Vetter , stable@vger.kernel.org Subject: [PATCH] drm/i915: Enable display WA#1183 from its correct spot Date: Thu, 19 Apr 2018 18:51:09 +0300 Message-Id: <20180419155109.29451-1-imre.deak@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: The DMC FW specific part of display WA#1183 is supposed to be enabled whenever enabling DC5 or DC6, so move it to the DC6 enable function from the DC6 disable function. I noticed this after Daniel's patch to remove the unused skl_disable_dc6() function. Fixes: 53421c2fe99c ("drm/i915: Apply Display WA #1183 on skl, kbl, and cfl") Cc: Lucas De Marchi Cc: Rodrigo Vivi Cc: Ville Syrjälä Cc: Daniel Vetter Cc: Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 53ea564f971e..66de4b2dc8b7 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -641,19 +641,18 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv) DRM_DEBUG_KMS("Enabling DC6\n"); - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); + /* Wa Display #1183: skl,kbl,cfl */ + if (IS_GEN9_BC(dev_priv)) + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | + SKL_SELECT_ALTERNATE_DC_EXIT); + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); } void skl_disable_dc6(struct drm_i915_private *dev_priv) { DRM_DEBUG_KMS("Disabling DC6\n"); - /* Wa Display #1183: skl,kbl,cfl */ - if (IS_GEN9_BC(dev_priv)) - I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | - SKL_SELECT_ALTERNATE_DC_EXIT); - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); } -- 2.13.2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: [PATCH] drm/i915: Enable display WA#1183 from its correct spot Date: Thu, 19 Apr 2018 18:51:09 +0300 Message-ID: <20180419155109.29451-1-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 99FB06E084 for ; Thu, 19 Apr 2018 15:51:44 +0000 (UTC) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , Lucas De Marchi , stable@vger.kernel.org, Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org VGhlIERNQyBGVyBzcGVjaWZpYyBwYXJ0IG9mIGRpc3BsYXkgV0EjMTE4MyBpcyBzdXBwb3NlZCB0 byBiZSBlbmFibGVkCndoZW5ldmVyIGVuYWJsaW5nIERDNSBvciBEQzYsIHNvIG1vdmUgaXQgdG8g dGhlIERDNiBlbmFibGUgZnVuY3Rpb24KZnJvbSB0aGUgREM2IGRpc2FibGUgZnVuY3Rpb24uCgpJ IG5vdGljZWQgdGhpcyBhZnRlciBEYW5pZWwncyBwYXRjaCB0byByZW1vdmUgdGhlIHVudXNlZApz a2xfZGlzYWJsZV9kYzYoKSBmdW5jdGlvbi4KCkZpeGVzOiA1MzQyMWMyZmU5OWMgKCJkcm0vaTkx NTogQXBwbHkgRGlzcGxheSBXQSAjMTE4MyBvbiBza2wsIGtibCwgYW5kIGNmbCIpCkNjOiBMdWNh cyBEZSBNYXJjaGkgPGx1Y2FzLmRlbWFyY2hpQGludGVsLmNvbT4KQ2M6IFJvZHJpZ28gVml2aSA8 cm9kcmlnby52aXZpQGludGVsLmNvbT4KQ2M6IFZpbGxlIFN5cmrDpGzDpCA8dmlsbGUuc3lyamFs YUBsaW51eC5pbnRlbC5jb20+CkNjOiBEYW5pZWwgVmV0dGVyIDxkYW5pZWwudmV0dGVyQGZmd2xs LmNoPgpDYzogPHN0YWJsZUB2Z2VyLmtlcm5lbC5vcmc+ClNpZ25lZC1vZmYtYnk6IEltcmUgRGVh ayA8aW1yZS5kZWFrQGludGVsLmNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9y dW50aW1lX3BtLmMgfCAxMSArKysrKy0tLS0tLQogMSBmaWxlIGNoYW5nZWQsIDUgaW5zZXJ0aW9u cygrKSwgNiBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9p bnRlbF9ydW50aW1lX3BtLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9ydW50aW1lX3Bt LmMKaW5kZXggNTNlYTU2NGY5NzFlLi42NmRlNGIyZGM4YjcgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMv Z3B1L2RybS9pOTE1L2ludGVsX3J1bnRpbWVfcG0uYworKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkx NS9pbnRlbF9ydW50aW1lX3BtLmMKQEAgLTY0MSwxOSArNjQxLDE4IEBAIHZvaWQgc2tsX2VuYWJs ZV9kYzYoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2KQogCiAJRFJNX0RFQlVHX0tN UygiRW5hYmxpbmcgREM2XG4iKTsKIAotCWdlbjlfc2V0X2RjX3N0YXRlKGRldl9wcml2LCBEQ19T VEFURV9FTl9VUFRPX0RDNik7CisJLyogV2EgRGlzcGxheSAjMTE4Mzogc2tsLGtibCxjZmwgKi8K KwlpZiAoSVNfR0VOOV9CQyhkZXZfcHJpdikpCisJCUk5MTVfV1JJVEUoR0VOOF9DSElDS0VOX0RD UFJfMSwgSTkxNV9SRUFEKEdFTjhfQ0hJQ0tFTl9EQ1BSXzEpIHwKKwkJCSAgIFNLTF9TRUxFQ1Rf QUxURVJOQVRFX0RDX0VYSVQpOwogCisJZ2VuOV9zZXRfZGNfc3RhdGUoZGV2X3ByaXYsIERDX1NU QVRFX0VOX1VQVE9fREM2KTsKIH0KIAogdm9pZCBza2xfZGlzYWJsZV9kYzYoc3RydWN0IGRybV9p OTE1X3ByaXZhdGUgKmRldl9wcml2KQogewogCURSTV9ERUJVR19LTVMoIkRpc2FibGluZyBEQzZc biIpOwogCi0JLyogV2EgRGlzcGxheSAjMTE4Mzogc2tsLGtibCxjZmwgKi8KLQlpZiAoSVNfR0VO OV9CQyhkZXZfcHJpdikpCi0JCUk5MTVfV1JJVEUoR0VOOF9DSElDS0VOX0RDUFJfMSwgSTkxNV9S RUFEKEdFTjhfQ0hJQ0tFTl9EQ1BSXzEpIHwKLQkJCSAgIFNLTF9TRUxFQ1RfQUxURVJOQVRFX0RD X0VYSVQpOwotCiAJZ2VuOV9zZXRfZGNfc3RhdGUoZGV2X3ByaXYsIERDX1NUQVRFX0RJU0FCTEUp OwogfQogCi0tIAoyLjEzLjIKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNr dG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2lu dGVsLWdmeAo=