Re: Setting up a call to discuss PCI Emulation - Future Direction

From: Alexey G <x1917x@gmail.com>
To: "Roger Pau Monné" <roger.pau@citrix.com>
Cc: Lars Kurth <lars.kurth@citrix.com>,
	Stefano Stabellini <sstabellini@kernel.org>,
	Daniel Smith <dpsmith@apertussolutions.com>,
	Christopher Clark <christopher.w.clark@gmail.com>,
	Rich Persaud <persaur@gmail.com>,
	Julien Grall <julien.grall@arm.com>,
	Paul Durrant <Paul.Durrant@citrix.com>,
	xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: Setting up a call to discuss PCI Emulation - Future Direction
Date: Sat, 21 Apr 2018 14:47:16 +1000	[thread overview]
Message-ID: <20180421144716.000007be@gmail.com> (raw)
In-Reply-To: <20180413100149.33jiaddx5spfblmd@MacBook-Pro-de-Roger.local>

On Fri, 13 Apr 2018 11:01:49 +0100
Roger Pau Monné <roger.pau@citrix.com> wrote:

>On Thu, Apr 12, 2018 at 05:50:00PM +0100, Lars Kurth wrote:
>> 
>> 
>> On 12/04/2018, 17:41, "Roger Pau Monne" <roger.pau@citrix.com>
>> wrote:
>> 
>>     On Thu, Apr 12, 2018 at 05:32:57PM +0100, Lars Kurth wrote:
>> 
>>   
>>     >    may work. For me Mon, Wed and Fri’s generally work at those
>>     > time-slots. Next week is a little busy for me, so I would
>>     > prefer the following week. If you could fill out the following
>>     > Google poll, if this week works that would be great. Otherwise
>>     > please scream.  
>>     
>>     I'm afraid I'm on vacations from the 21st to the 29th of April,
>> so I won't be able to join the meeting unless we move it to the week
>> after. Let's see what people think of the current dates.
>>     
>>     Roger.
>>     
>> Hi, I changed the dates to the week after. Poll so far has been
>> invalidated.
>> 
>> See https://doodle.com/poll/gdnmcrvnibmw563n  
>
>Thanks! I've already fixed my vote.
>
>I guess this will come later, but we need a clear agenda of items
>because the x86 and ARM topics are probably going to be completely
>different (albeit all related to PCI).
>
>Roger.

1. different approaches to handle some critical chipset-specific
   registers (MCH PCIEXBAR first of all), currently emulated by
   QEMU. Role of QEMU in the emulation of MMCONFIG accesses.

2. MMIO hole sizing in general (for HVM) -- in which PT usecases this is
   needed, requirements, limitations. It is related to the emulated
   chipset-specific resources and depends on the chosen solution for #1.

I'll try to describe different possible implementations how to make the
multiple PCI device emulators feature compatible with emulated MMCONFIG
before the meeting, to have a ground for discussion. There are at least
3 possible directions currently to solve this problem.

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