From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751558AbeDYFtD (ORCPT ); Wed, 25 Apr 2018 01:49:03 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:35094 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751350AbeDYFtA (ORCPT ); Wed, 25 Apr 2018 01:49:00 -0400 Date: Tue, 24 Apr 2018 22:48:55 -0700 From: Christoph Hellwig To: Daniel Vetter Cc: Christoph Hellwig , Christian =?iso-8859-1?Q?K=F6nig?= , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Linux Kernel Mailing List , amd-gfx list , Jerome Glisse , dri-devel , Dan Williams , Logan Gunthorpe , "open list:DMA BUFFER SHARING FRAMEWORK" Subject: Re: [Linaro-mm-sig] [PATCH 4/8] dma-buf: add peer2peer flag Message-ID: <20180425054855.GA17038@infradead.org> References: <20180419081657.GA16735@infradead.org> <20180420071312.GF31310@phenom.ffwll.local> <3e17afc5-7d6c-5795-07bd-f23e34cf8d4b@gmail.com> <20180420101755.GA11400@infradead.org> <20180420124625.GA31078@infradead.org> <20180420152111.GR31310@phenom.ffwll.local> <20180424184847.GA3247@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.2 (2017-12-15) X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 24, 2018 at 09:32:20PM +0200, Daniel Vetter wrote: > Out of curiosity, how much virtual flushing stuff is there still out > there? At least in drm we've pretty much ignore this, and seem to be > getting away without a huge uproar (at least from driver developers > and users, core folks are less amused about that). As I've just been wading through the code, the following architectures have non-coherent dma that flushes by virtual address for at least some platforms: - arm [1], arm64, hexagon, nds32, nios2, parisc, sh, xtensa, mips, powerpc These have non-coherent dma ops that flush by physical address: - arc, arm [1], c6x, m68k, microblaze, openrisc, sparc And these do not have non-coherent dma ops at all: - alpha, h8300, riscv, unicore32, x86 [1] arm Ń•eems to do both virtually and physically based ops, further audit needed. Note that using virtual addresses in the cache flushing interface doesn't mean that the cache actually is virtually indexed, but it at least allows for the possibility. > > I think the most important thing about such a buffer object is that > > it can distinguish the underlying mapping types. While > > dma_alloc_coherent, dma_alloc_attrs with DMA_ATTR_NON_CONSISTENT, > > dma_map_page/dma_map_single/dma_map_sg and dma_map_resource all give > > back a dma_addr_t they are in now way interchangable. And trying to > > stuff them all into a structure like struct scatterlist that has > > no indication what kind of mapping you are dealing with is just > > asking for trouble. > > Well the idea was to have 1 interface to allow all drivers to share > buffers with anything else, no matter how exactly they're allocated. Isn't that interface supposed to be dmabuf? Currently dma_map leaks a scatterlist through the sg_table in dma_buf_map_attachment / ->map_dma_buf, but looking at a few of the callers it seems like they really do not even want a scatterlist to start with, but check that is contains a physically contiguous range first. So kicking the scatterlist our there will probably improve the interface in general. > dma-buf has all the functions for flushing, so you can have coherent > mappings, non-coherent mappings and pretty much anything else. Or well > could, because in practice people hack up layering violations until it > works for the 2-3 drivers they care about. On top of that there's the > small issue that x86 insists that dma is coherent (and that's true for > most devices, including v4l drivers you might want to share stuff > with), and gpus really, really really do want to make almost > everything incoherent. How do discrete GPUs manage to be incoherent when attached over PCIe? From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [Linaro-mm-sig] [PATCH 4/8] dma-buf: add peer2peer flag Date: Tue, 24 Apr 2018 22:48:55 -0700 Message-ID: <20180425054855.GA17038@infradead.org> References: <20180419081657.GA16735@infradead.org> <20180420071312.GF31310@phenom.ffwll.local> <3e17afc5-7d6c-5795-07bd-f23e34cf8d4b@gmail.com> <20180420101755.GA11400@infradead.org> <20180420124625.GA31078@infradead.org> <20180420152111.GR31310@phenom.ffwll.local> <20180424184847.GA3247@infradead.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Daniel Vetter Cc: "moderated list:DMA BUFFER SHARING FRAMEWORK" , Linux Kernel Mailing List , amd-gfx list , Christoph Hellwig , Jerome Glisse , dri-devel , Dan Williams , Logan Gunthorpe , Christian =?iso-8859-1?Q?K=F6nig?= , "open list:DMA BUFFER SHARING FRAMEWORK" List-Id: dri-devel@lists.freedesktop.org T24gVHVlLCBBcHIgMjQsIDIwMTggYXQgMDk6MzI6MjBQTSArMDIwMCwgRGFuaWVsIFZldHRlciB3 cm90ZToKPiBPdXQgb2YgY3VyaW9zaXR5LCBob3cgbXVjaCB2aXJ0dWFsIGZsdXNoaW5nIHN0dWZm IGlzIHRoZXJlIHN0aWxsIG91dAo+IHRoZXJlPyBBdCBsZWFzdCBpbiBkcm0gd2UndmUgcHJldHR5 IG11Y2ggaWdub3JlIHRoaXMsIGFuZCBzZWVtIHRvIGJlCj4gZ2V0dGluZyBhd2F5IHdpdGhvdXQg YSBodWdlIHVwcm9hciAoYXQgbGVhc3QgZnJvbSBkcml2ZXIgZGV2ZWxvcGVycwo+IGFuZCB1c2Vy cywgY29yZSBmb2xrcyBhcmUgbGVzcyBhbXVzZWQgYWJvdXQgdGhhdCkuCgpBcyBJJ3ZlIGp1c3Qg YmVlbiB3YWRpbmcgdGhyb3VnaCB0aGUgY29kZSwgdGhlIGZvbGxvd2luZyBhcmNoaXRlY3R1cmVz CmhhdmUgbm9uLWNvaGVyZW50IGRtYSB0aGF0IGZsdXNoZXMgYnkgdmlydHVhbCBhZGRyZXNzIGZv ciBhdCBsZWFzdCBzb21lCnBsYXRmb3JtczoKCiAtIGFybSBbMV0sIGFybTY0LCBoZXhhZ29uLCBu ZHMzMiwgbmlvczIsIHBhcmlzYywgc2gsIHh0ZW5zYSwgbWlwcywKICAgcG93ZXJwYwoKVGhlc2Ug aGF2ZSBub24tY29oZXJlbnQgZG1hIG9wcyB0aGF0IGZsdXNoIGJ5IHBoeXNpY2FsIGFkZHJlc3M6 CgogLSBhcmMsIGFybSBbMV0sIGM2eCwgbTY4aywgbWljcm9ibGF6ZSwgb3BlbnJpc2MsIHNwYXJj CgpBbmQgdGhlc2UgZG8gbm90IGhhdmUgbm9uLWNvaGVyZW50IGRtYSBvcHMgYXQgYWxsOgoKIC0g YWxwaGEsIGg4MzAwLCByaXNjdiwgdW5pY29yZTMyLCB4ODYKClsxXSBhcm0g0ZVlZW1zIHRvIGRv IGJvdGggdmlydHVhbGx5IGFuZCBwaHlzaWNhbGx5IGJhc2VkIG9wcywgZnVydGhlcgphdWRpdCBu ZWVkZWQuCgpOb3RlIHRoYXQgdXNpbmcgdmlydHVhbCBhZGRyZXNzZXMgaW4gdGhlIGNhY2hlIGZs dXNoaW5nIGludGVyZmFjZQpkb2Vzbid0IG1lYW4gdGhhdCB0aGUgY2FjaGUgYWN0dWFsbHkgaXMg dmlydHVhbGx5IGluZGV4ZWQsIGJ1dCBpdCBhdApsZWFzdCBhbGxvd3MgZm9yIHRoZSBwb3NzaWJp bGl0eS4KCj4gPiBJIHRoaW5rIHRoZSBtb3N0IGltcG9ydGFudCB0aGluZyBhYm91dCBzdWNoIGEg YnVmZmVyIG9iamVjdCBpcyB0aGF0Cj4gPiBpdCBjYW4gZGlzdGluZ3Vpc2ggdGhlIHVuZGVybHlp bmcgbWFwcGluZyB0eXBlcy4gIFdoaWxlCj4gPiBkbWFfYWxsb2NfY29oZXJlbnQsIGRtYV9hbGxv Y19hdHRycyB3aXRoIERNQV9BVFRSX05PTl9DT05TSVNURU5ULAo+ID4gZG1hX21hcF9wYWdlL2Rt YV9tYXBfc2luZ2xlL2RtYV9tYXBfc2cgYW5kIGRtYV9tYXBfcmVzb3VyY2UgYWxsIGdpdmUKPiA+ IGJhY2sgYSBkbWFfYWRkcl90IHRoZXkgYXJlIGluIG5vdyB3YXkgaW50ZXJjaGFuZ2FibGUuICBB bmQgdHJ5aW5nIHRvCj4gPiBzdHVmZiB0aGVtIGFsbCBpbnRvIGEgc3RydWN0dXJlIGxpa2Ugc3Ry dWN0IHNjYXR0ZXJsaXN0IHRoYXQgaGFzCj4gPiBubyBpbmRpY2F0aW9uIHdoYXQga2luZCBvZiBt YXBwaW5nIHlvdSBhcmUgZGVhbGluZyB3aXRoIGlzIGp1c3QKPiA+IGFza2luZyBmb3IgdHJvdWJs ZS4KPiAKPiBXZWxsIHRoZSBpZGVhIHdhcyB0byBoYXZlIDEgaW50ZXJmYWNlIHRvIGFsbG93IGFs bCBkcml2ZXJzIHRvIHNoYXJlCj4gYnVmZmVycyB3aXRoIGFueXRoaW5nIGVsc2UsIG5vIG1hdHRl ciBob3cgZXhhY3RseSB0aGV5J3JlIGFsbG9jYXRlZC4KCklzbid0IHRoYXQgaW50ZXJmYWNlIHN1 cHBvc2VkIHRvIGJlIGRtYWJ1Zj8gIEN1cnJlbnRseSBkbWFfbWFwIGxlYWtzCmEgc2NhdHRlcmxp c3QgdGhyb3VnaCB0aGUgc2dfdGFibGUgaW4gZG1hX2J1Zl9tYXBfYXR0YWNobWVudCAvCi0+bWFw X2RtYV9idWYsIGJ1dCBsb29raW5nIGF0IGEgZmV3IG9mIHRoZSBjYWxsZXJzIGl0IHNlZW1zIGxp a2UgdGhleQpyZWFsbHkgZG8gbm90IGV2ZW4gd2FudCBhIHNjYXR0ZXJsaXN0IHRvIHN0YXJ0IHdp dGgsIGJ1dCBjaGVjayB0aGF0CmlzIGNvbnRhaW5zIGEgcGh5c2ljYWxseSBjb250aWd1b3VzIHJh bmdlIGZpcnN0LiAgU28ga2lja2luZyB0aGUKc2NhdHRlcmxpc3Qgb3VyIHRoZXJlIHdpbGwgcHJv YmFibHkgaW1wcm92ZSB0aGUgaW50ZXJmYWNlIGluIGdlbmVyYWwuCgo+IGRtYS1idWYgaGFzIGFs bCB0aGUgZnVuY3Rpb25zIGZvciBmbHVzaGluZywgc28geW91IGNhbiBoYXZlIGNvaGVyZW50Cj4g bWFwcGluZ3MsIG5vbi1jb2hlcmVudCBtYXBwaW5ncyBhbmQgcHJldHR5IG11Y2ggYW55dGhpbmcg ZWxzZS4gT3Igd2VsbAo+IGNvdWxkLCBiZWNhdXNlIGluIHByYWN0aWNlIHBlb3BsZSBoYWNrIHVw IGxheWVyaW5nIHZpb2xhdGlvbnMgdW50aWwgaXQKPiB3b3JrcyBmb3IgdGhlIDItMyBkcml2ZXJz IHRoZXkgY2FyZSBhYm91dC4gT24gdG9wIG9mIHRoYXQgdGhlcmUncyB0aGUKPiBzbWFsbCBpc3N1 ZSB0aGF0IHg4NiBpbnNpc3RzIHRoYXQgZG1hIGlzIGNvaGVyZW50IChhbmQgdGhhdCdzIHRydWUg Zm9yCj4gbW9zdCBkZXZpY2VzLCBpbmNsdWRpbmcgdjRsIGRyaXZlcnMgeW91IG1pZ2h0IHdhbnQg dG8gc2hhcmUgc3R1ZmYKPiB3aXRoKSwgYW5kIGdwdXMgcmVhbGx5LCByZWFsbHkgcmVhbGx5IGRv IHdhbnQgdG8gbWFrZSBhbG1vc3QKPiBldmVyeXRoaW5nIGluY29oZXJlbnQuCgpIb3cgZG8gZGlz Y3JldGUgR1BVcyBtYW5hZ2UgdG8gYmUgaW5jb2hlcmVudCB3aGVuIGF0dGFjaGVkIG92ZXIgUENJ ZT8KX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRl dmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8v bGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==