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x-vs=clean score=-100 state=0 X-ME-VSCategory: clean X-CM-Envelope: MS4wfMmg3MgLB2HJvNl9w+6lGGygi2Yp+QU3EExZYiQIL/mLB1nwnTY2pmQfyAwcp3wH53GXYSgBrCKFXW7rNsT3k+b66crPSVxgS+4B0GIyltPPKtbsWdYN rM+nXh24MqL07hhC2mVas0bvYnp931Hny6QYaTSYVj0SWxgqebeY9XaPWHTX7wFXl6gHh2Znmbwv/D7fCIHfuejxdQ2I8AgBNlrXfDxcSl5vxdPpnvac4lDe X-CM-Analysis: v=2.3 cv=FKU1Odgs c=1 sm=1 tr=0 a=UK1r566ZdBxH71SXbqIOeA==:117 a=UK1r566ZdBxH71SXbqIOeA==:17 a=kj9zAlcOel0A:10 a=Kd1tUaAdevIA:10 a=tA7aZXjiAAAA:8 a=GQPbXzJ74lNKkey2py4A:9 a=CjuIK1q_8ugA:10 a=kIIFJ0VLUOy1gFZzwZHL:22 X-ME-CMScore: 0 X-ME-CMCategory: none Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753793AbeDZUHk (ORCPT ); Thu, 26 Apr 2018 16:07:40 -0400 Received: from 8bytes.org ([81.169.241.247]:54596 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752418AbeDZUHj (ORCPT ); Thu, 26 Apr 2018 16:07:39 -0400 Date: Thu, 26 Apr 2018 22:07:37 +0200 From: "joro@8bytes.org" To: "Kani, Toshi" Cc: "linux-kernel@vger.kernel.org" , "bp@suse.de" , "tglx@linutronix.de" , "linux-mm@kvack.org" , "guohanjun@huawei.com" , "wxf.wang@hisilicon.com" , "stable@vger.kernel.org" , "x86@kernel.org" , "akpm@linux-foundation.org" , "willy@infradead.org" , "hpa@zytor.com" , "catalin.marinas@arm.com" , "mingo@redhat.com" , "will.deacon@arm.com" , "Hocko, Michal" , "cpandya@codeaurora.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v2 2/2] x86/mm: implement free pmd/pte page interfaces Message-ID: <20180426200737.GS15462@8bytes.org> References: <20180314180155.19492-1-toshi.kani@hpe.com> <20180314180155.19492-3-toshi.kani@hpe.com> <20180426141926.GN15462@8bytes.org> <1524759629.2693.465.camel@hpe.com> <20180426172327.GQ15462@8bytes.org> <1524764948.2693.478.camel@hpe.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1524764948.2693.478.camel@hpe.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Thu, Apr 26, 2018 at 05:49:58PM +0000, Kani, Toshi wrote: > On Thu, 2018-04-26 at 19:23 +0200, joro@8bytes.org wrote: > > So the PMD entry you clear can still be in a page-walk cache and this > > needs to be flushed too before you can free the PTE page. Otherwise > > page-walks might still go to the page you just freed. That is especially > > bad when the page is already reallocated and filled with other data. > > I do not understand why we need to flush processor caches here. x86 > processor caches are coherent with MESI. So, clearing an PMD entry > modifies a cache entry on the processor associated with the address, > which in turn invalidates all stale cache entries on other processors. A page walk cache is not about the processors data cache, its a cache similar to the TLB to speed up page-walks by caching intermediate results of previous page walks. Thanks, Joerg From mboxrd@z Thu Jan 1 00:00:00 1970 From: joro@8bytes.org (joro at 8bytes.org) Date: Thu, 26 Apr 2018 22:07:37 +0200 Subject: [PATCH v2 2/2] x86/mm: implement free pmd/pte page interfaces In-Reply-To: <1524764948.2693.478.camel@hpe.com> References: <20180314180155.19492-1-toshi.kani@hpe.com> <20180314180155.19492-3-toshi.kani@hpe.com> <20180426141926.GN15462@8bytes.org> <1524759629.2693.465.camel@hpe.com> <20180426172327.GQ15462@8bytes.org> <1524764948.2693.478.camel@hpe.com> Message-ID: <20180426200737.GS15462@8bytes.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Apr 26, 2018 at 05:49:58PM +0000, Kani, Toshi wrote: > On Thu, 2018-04-26 at 19:23 +0200, joro at 8bytes.org wrote: > > So the PMD entry you clear can still be in a page-walk cache and this > > needs to be flushed too before you can free the PTE page. Otherwise > > page-walks might still go to the page you just freed. That is especially > > bad when the page is already reallocated and filled with other data. > > I do not understand why we need to flush processor caches here. x86 > processor caches are coherent with MESI. So, clearing an PMD entry > modifies a cache entry on the processor associated with the address, > which in turn invalidates all stale cache entries on other processors. A page walk cache is not about the processors data cache, its a cache similar to the TLB to speed up page-walks by caching intermediate results of previous page walks. Thanks, Joerg