* [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: David S. Miller, netdev
Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring,
Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-arm-kernel, linux-kernel, devicetree
Due to the dwmac glue layer register changed, we need to
introduce a new compatible name for the Meson-AXG SoC
to support for the RMII 100M ethernet PHY.
Change since v1 at [1]:
- implement set_phy_mode() for each SoC
[1] https://lkml.kernel.org/r/20180426160508.29380-1-yixun.lan@amlogic.com
Yixun Lan (2):
dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
net: stmmac: dwmac-meson: extend phy mode setting
.../devicetree/bindings/net/meson-dwmac.txt | 1 +
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
2 files changed, 105 insertions(+), 16 deletions(-)
--
2.17.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: David S. Miller, netdev
Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring,
Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-arm-kernel, linux-kernel, devicetree
Due to the dwmac glue layer register changed, we need to
introduce a new compatible name for the Meson-AXG SoC
to support for the RMII 100M ethernet PHY.
Change since v1 at [1]:
- implement set_phy_mode() for each SoC
[1] https://lkml.kernel.org/r/20180426160508.29380-1-yixun.lan@amlogic.com
Yixun Lan (2):
dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
net: stmmac: dwmac-meson: extend phy mode setting
.../devicetree/bindings/net/meson-dwmac.txt | 1 +
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
2 files changed, 105 insertions(+), 16 deletions(-)
--
2.17.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: linux-arm-kernel
Due to the dwmac glue layer register changed, we need to
introduce a new compatible name for the Meson-AXG SoC
to support for the RMII 100M ethernet PHY.
Change since v1 at [1]:
- implement set_phy_mode() for each SoC
[1] https://lkml.kernel.org/r/20180426160508.29380-1-yixun.lan at amlogic.com
Yixun Lan (2):
dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
net: stmmac: dwmac-meson: extend phy mode setting
.../devicetree/bindings/net/meson-dwmac.txt | 1 +
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
2 files changed, 105 insertions(+), 16 deletions(-)
--
2.17.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: linus-amlogic
Due to the dwmac glue layer register changed, we need to
introduce a new compatible name for the Meson-AXG SoC
to support for the RMII 100M ethernet PHY.
Change since v1 at [1]:
- implement set_phy_mode() for each SoC
[1] https://lkml.kernel.org/r/20180426160508.29380-1-yixun.lan at amlogic.com
Yixun Lan (2):
dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
net: stmmac: dwmac-meson: extend phy mode setting
.../devicetree/bindings/net/meson-dwmac.txt | 1 +
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
2 files changed, 105 insertions(+), 16 deletions(-)
--
2.17.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
2018-04-28 10:21 ` Yixun Lan
(?)
(?)
@ 2018-04-28 10:21 ` Yixun Lan
-1 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: David S. Miller, netdev
Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring,
Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-arm-kernel, linux-kernel, devicetree
We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index 61cada22ae6c..1321bb194ed9 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -11,6 +11,7 @@ Required properties on all platforms:
- "amlogic,meson8b-dwmac"
- "amlogic,meson8m2-dwmac"
- "amlogic,meson-gxbb-dwmac"
+ - "amlogic,meson-axg-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
should be used.
--
2.17.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: David S. Miller, netdev
Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring,
Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-arm-kernel, linux-kernel, devicetree
We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index 61cada22ae6c..1321bb194ed9 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -11,6 +11,7 @@ Required properties on all platforms:
- "amlogic,meson8b-dwmac"
- "amlogic,meson8m2-dwmac"
- "amlogic,meson-gxbb-dwmac"
+ - "amlogic,meson-axg-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
should be used.
--
2.17.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: linux-arm-kernel
We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index 61cada22ae6c..1321bb194ed9 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -11,6 +11,7 @@ Required properties on all platforms:
- "amlogic,meson8b-dwmac"
- "amlogic,meson8m2-dwmac"
- "amlogic,meson-gxbb-dwmac"
+ - "amlogic,meson-axg-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
should be used.
--
2.17.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: linus-amlogic
We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index 61cada22ae6c..1321bb194ed9 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -11,6 +11,7 @@ Required properties on all platforms:
- "amlogic,meson8b-dwmac"
- "amlogic,meson8m2-dwmac"
- "amlogic,meson-gxbb-dwmac"
+ - "amlogic,meson-axg-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
should be used.
--
2.17.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/2] net: stmmac: dwmac-meson: extend phy mode setting
2018-04-28 10:21 ` Yixun Lan
(?)
@ 2018-04-28 10:21 ` Yixun Lan
-1 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: David S. Miller, netdev
Cc: Yixun Lan, Kevin Hilman, Carlo Caione, Rob Herring,
Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-arm-kernel, linux-kernel
In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
is extended from bit[0] to bit[2:0].
There is no problem if we configure it to the RGMII 1000M PHY mode,
since the register setting is coincidentally compatible with previous one,
but for the RMII 100M PHY mode, the configuration need to be changed to
value - b100.
This patch was verified with a RTL8201F 100M ethernet PHY.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
1 file changed, 104 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 7cb794094a70..4ff231df7322 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -18,6 +18,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/of_net.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
@@ -29,6 +30,10 @@
#define PRG_ETH0_RGMII_MODE BIT(0)
+#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
+#define PRG_ETH0_EXT_RGMII_MODE 1
+#define PRG_ETH0_EXT_RMII_MODE 4
+
/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
#define PRG_ETH0_CLK_M250_SEL_SHIFT 4
#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
@@ -47,12 +52,20 @@
#define MUX_CLK_NUM_PARENTS 2
+struct meson8b_dwmac;
+
+struct meson8b_dwmac_data {
+ int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
+};
+
struct meson8b_dwmac {
- struct device *dev;
- void __iomem *regs;
- phy_interface_t phy_mode;
- struct clk *rgmii_tx_clk;
- u32 tx_delay_ns;
+ struct device *dev;
+ void __iomem *regs;
+
+ const struct meson8b_dwmac_data *data;
+ phy_interface_t phy_mode;
+ struct clk *rgmii_tx_clk;
+ u32 tx_delay_ns;
};
struct meson8b_dwmac_clk_configs {
@@ -171,6 +184,59 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
return 0;
}
+static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
+{
+ switch (dwmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* enable RGMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_RGMII_MODE,
+ PRG_ETH0_RGMII_MODE);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ /* disable RGMII mode -> enables RMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_RGMII_MODE, 0);
+ break;
+ default:
+ dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+ phy_modes(dwmac->phy_mode));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
+{
+ switch (dwmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* enable RGMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RGMII_MODE);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ /* disable RGMII mode -> enables RMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RMII_MODE);
+ break;
+ default:
+ dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+ phy_modes(dwmac->phy_mode));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
{
int ret;
@@ -188,10 +254,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
- /* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
- PRG_ETH0_RGMII_MODE);
-
/* only relevant for RMII mode -> disable in RGMII mode */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
PRG_ETH0_INVERTED_RMII_CLK, 0);
@@ -224,10 +286,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
break;
case PHY_INTERFACE_MODE_RMII:
- /* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
- 0);
-
/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
PRG_ETH0_INVERTED_RMII_CLK,
@@ -274,6 +332,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
goto err_remove_config_dt;
}
+ dwmac->data = (const struct meson8b_dwmac_data *)
+ of_device_get_match_data(&pdev->dev);
+ if (!dwmac->data)
+ return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(dwmac->regs)) {
@@ -298,6 +361,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
if (ret)
goto err_remove_config_dt;
+ ret = dwmac->data->set_phy_mode(dwmac);
+ if (ret)
+ goto err_remove_config_dt;
+
ret = meson8b_init_prg_eth(dwmac);
if (ret)
goto err_remove_config_dt;
@@ -316,10 +383,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
return ret;
}
+static const struct meson8b_dwmac_data meson8b_dwmac_data = {
+ .set_phy_mode = meson8b_set_phy_mode,
+};
+
+static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
+ .set_phy_mode = meson_axg_set_phy_mode,
+};
+
static const struct of_device_id meson8b_dwmac_match[] = {
- { .compatible = "amlogic,meson8b-dwmac" },
- { .compatible = "amlogic,meson8m2-dwmac" },
- { .compatible = "amlogic,meson-gxbb-dwmac" },
+ {
+ .compatible = "amlogic,meson8b-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson8m2-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson-gxbb-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson-axg-dwmac",
+ .data = &meson_axg_dwmac_data,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
--
2.17.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/2] net: stmmac: dwmac-meson: extend phy mode setting
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: linux-arm-kernel
In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
is extended from bit[0] to bit[2:0].
There is no problem if we configure it to the RGMII 1000M PHY mode,
since the register setting is coincidentally compatible with previous one,
but for the RMII 100M PHY mode, the configuration need to be changed to
value - b100.
This patch was verified with a RTL8201F 100M ethernet PHY.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
1 file changed, 104 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 7cb794094a70..4ff231df7322 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -18,6 +18,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/of_net.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
@@ -29,6 +30,10 @@
#define PRG_ETH0_RGMII_MODE BIT(0)
+#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
+#define PRG_ETH0_EXT_RGMII_MODE 1
+#define PRG_ETH0_EXT_RMII_MODE 4
+
/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
#define PRG_ETH0_CLK_M250_SEL_SHIFT 4
#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
@@ -47,12 +52,20 @@
#define MUX_CLK_NUM_PARENTS 2
+struct meson8b_dwmac;
+
+struct meson8b_dwmac_data {
+ int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
+};
+
struct meson8b_dwmac {
- struct device *dev;
- void __iomem *regs;
- phy_interface_t phy_mode;
- struct clk *rgmii_tx_clk;
- u32 tx_delay_ns;
+ struct device *dev;
+ void __iomem *regs;
+
+ const struct meson8b_dwmac_data *data;
+ phy_interface_t phy_mode;
+ struct clk *rgmii_tx_clk;
+ u32 tx_delay_ns;
};
struct meson8b_dwmac_clk_configs {
@@ -171,6 +184,59 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
return 0;
}
+static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
+{
+ switch (dwmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* enable RGMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_RGMII_MODE,
+ PRG_ETH0_RGMII_MODE);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ /* disable RGMII mode -> enables RMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_RGMII_MODE, 0);
+ break;
+ default:
+ dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+ phy_modes(dwmac->phy_mode));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
+{
+ switch (dwmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* enable RGMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RGMII_MODE);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ /* disable RGMII mode -> enables RMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RMII_MODE);
+ break;
+ default:
+ dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+ phy_modes(dwmac->phy_mode));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
{
int ret;
@@ -188,10 +254,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
- /* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
- PRG_ETH0_RGMII_MODE);
-
/* only relevant for RMII mode -> disable in RGMII mode */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
PRG_ETH0_INVERTED_RMII_CLK, 0);
@@ -224,10 +286,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
break;
case PHY_INTERFACE_MODE_RMII:
- /* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
- 0);
-
/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
PRG_ETH0_INVERTED_RMII_CLK,
@@ -274,6 +332,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
goto err_remove_config_dt;
}
+ dwmac->data = (const struct meson8b_dwmac_data *)
+ of_device_get_match_data(&pdev->dev);
+ if (!dwmac->data)
+ return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(dwmac->regs)) {
@@ -298,6 +361,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
if (ret)
goto err_remove_config_dt;
+ ret = dwmac->data->set_phy_mode(dwmac);
+ if (ret)
+ goto err_remove_config_dt;
+
ret = meson8b_init_prg_eth(dwmac);
if (ret)
goto err_remove_config_dt;
@@ -316,10 +383,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
return ret;
}
+static const struct meson8b_dwmac_data meson8b_dwmac_data = {
+ .set_phy_mode = meson8b_set_phy_mode,
+};
+
+static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
+ .set_phy_mode = meson_axg_set_phy_mode,
+};
+
static const struct of_device_id meson8b_dwmac_match[] = {
- { .compatible = "amlogic,meson8b-dwmac" },
- { .compatible = "amlogic,meson8m2-dwmac" },
- { .compatible = "amlogic,meson-gxbb-dwmac" },
+ {
+ .compatible = "amlogic,meson8b-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson8m2-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson-gxbb-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson-axg-dwmac",
+ .data = &meson_axg_dwmac_data,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
--
2.17.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/2] net: stmmac: dwmac-meson: extend phy mode setting
@ 2018-04-28 10:21 ` Yixun Lan
0 siblings, 0 replies; 20+ messages in thread
From: Yixun Lan @ 2018-04-28 10:21 UTC (permalink / raw)
To: linus-amlogic
In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
is extended from bit[0] to bit[2:0].
There is no problem if we configure it to the RGMII 1000M PHY mode,
since the register setting is coincidentally compatible with previous one,
but for the RMII 100M PHY mode, the configuration need to be changed to
value - b100.
This patch was verified with a RTL8201F 100M ethernet PHY.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
1 file changed, 104 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 7cb794094a70..4ff231df7322 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -18,6 +18,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/of_net.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
@@ -29,6 +30,10 @@
#define PRG_ETH0_RGMII_MODE BIT(0)
+#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
+#define PRG_ETH0_EXT_RGMII_MODE 1
+#define PRG_ETH0_EXT_RMII_MODE 4
+
/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
#define PRG_ETH0_CLK_M250_SEL_SHIFT 4
#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
@@ -47,12 +52,20 @@
#define MUX_CLK_NUM_PARENTS 2
+struct meson8b_dwmac;
+
+struct meson8b_dwmac_data {
+ int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
+};
+
struct meson8b_dwmac {
- struct device *dev;
- void __iomem *regs;
- phy_interface_t phy_mode;
- struct clk *rgmii_tx_clk;
- u32 tx_delay_ns;
+ struct device *dev;
+ void __iomem *regs;
+
+ const struct meson8b_dwmac_data *data;
+ phy_interface_t phy_mode;
+ struct clk *rgmii_tx_clk;
+ u32 tx_delay_ns;
};
struct meson8b_dwmac_clk_configs {
@@ -171,6 +184,59 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
return 0;
}
+static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
+{
+ switch (dwmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* enable RGMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_RGMII_MODE,
+ PRG_ETH0_RGMII_MODE);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ /* disable RGMII mode -> enables RMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_RGMII_MODE, 0);
+ break;
+ default:
+ dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+ phy_modes(dwmac->phy_mode));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
+{
+ switch (dwmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* enable RGMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RGMII_MODE);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ /* disable RGMII mode -> enables RMII mode */
+ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RMII_MODE);
+ break;
+ default:
+ dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+ phy_modes(dwmac->phy_mode));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
{
int ret;
@@ -188,10 +254,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
- /* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
- PRG_ETH0_RGMII_MODE);
-
/* only relevant for RMII mode -> disable in RGMII mode */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
PRG_ETH0_INVERTED_RMII_CLK, 0);
@@ -224,10 +286,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
break;
case PHY_INTERFACE_MODE_RMII:
- /* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
- 0);
-
/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
PRG_ETH0_INVERTED_RMII_CLK,
@@ -274,6 +332,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
goto err_remove_config_dt;
}
+ dwmac->data = (const struct meson8b_dwmac_data *)
+ of_device_get_match_data(&pdev->dev);
+ if (!dwmac->data)
+ return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(dwmac->regs)) {
@@ -298,6 +361,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
if (ret)
goto err_remove_config_dt;
+ ret = dwmac->data->set_phy_mode(dwmac);
+ if (ret)
+ goto err_remove_config_dt;
+
ret = meson8b_init_prg_eth(dwmac);
if (ret)
goto err_remove_config_dt;
@@ -316,10 +383,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
return ret;
}
+static const struct meson8b_dwmac_data meson8b_dwmac_data = {
+ .set_phy_mode = meson8b_set_phy_mode,
+};
+
+static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
+ .set_phy_mode = meson_axg_set_phy_mode,
+};
+
static const struct of_device_id meson8b_dwmac_match[] = {
- { .compatible = "amlogic,meson8b-dwmac" },
- { .compatible = "amlogic,meson8m2-dwmac" },
- { .compatible = "amlogic,meson-gxbb-dwmac" },
+ {
+ .compatible = "amlogic,meson8b-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson8m2-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson-gxbb-dwmac",
+ .data = &meson8b_dwmac_data,
+ },
+ {
+ .compatible = "amlogic,meson-axg-dwmac",
+ .data = &meson_axg_dwmac_data,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
--
2.17.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
2018-04-28 10:21 ` Yixun Lan
(?)
@ 2018-05-01 12:55 ` Rob Herring
-1 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2018-05-01 12:55 UTC (permalink / raw)
To: Yixun Lan
Cc: David S. Miller, netdev, Kevin Hilman, Carlo Caione,
Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-arm-kernel, linux-kernel, devicetree
On Sat, Apr 28, 2018 at 10:21:10AM +0000, Yixun Lan wrote:
> We need to introduce a new compatible name for the Meson-AXG SoC
> in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
> register of the dwmac glue layer is changed from previous old SoC.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
@ 2018-05-01 12:55 ` Rob Herring
0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2018-05-01 12:55 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Apr 28, 2018 at 10:21:10AM +0000, Yixun Lan wrote:
> We need to introduce a new compatible name for the Meson-AXG SoC
> in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
> register of the dwmac glue layer is changed from previous old SoC.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
@ 2018-05-01 12:55 ` Rob Herring
0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2018-05-01 12:55 UTC (permalink / raw)
To: linus-amlogic
On Sat, Apr 28, 2018 at 10:21:10AM +0000, Yixun Lan wrote:
> We need to introduce a new compatible name for the Meson-AXG SoC
> in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
> register of the dwmac glue layer is changed from previous old SoC.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/2] net: stmmac: dwmac-meson: extend phy mode setting
2018-04-28 10:21 ` Yixun Lan
(?)
@ 2018-05-01 13:20 ` Martin Blumenstingl
-1 siblings, 0 replies; 20+ messages in thread
From: Martin Blumenstingl @ 2018-05-01 13:20 UTC (permalink / raw)
To: Yixun Lan
Cc: David S. Miller, netdev, Kevin Hilman, Carlo Caione, Rob Herring,
Jerome Brunet, linux-amlogic, linux-arm-kernel, linux-kernel
Hello Yixun,
On Sat, Apr 28, 2018 at 12:21 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
> is extended from bit[0] to bit[2:0].
> There is no problem if we configure it to the RGMII 1000M PHY mode,
> since the register setting is coincidentally compatible with previous one,
> but for the RMII 100M PHY mode, the configuration need to be changed to
> value - b100.
> This patch was verified with a RTL8201F 100M ethernet PHY.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
> 1 file changed, 104 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> index 7cb794094a70..4ff231df7322 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> @@ -18,6 +18,7 @@
> #include <linux/io.h>
> #include <linux/ioport.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/of_net.h>
> #include <linux/mfd/syscon.h>
> #include <linux/platform_device.h>
> @@ -29,6 +30,10 @@
>
> #define PRG_ETH0_RGMII_MODE BIT(0)
>
> +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
> +#define PRG_ETH0_EXT_RGMII_MODE 1
> +#define PRG_ETH0_EXT_RMII_MODE 4
> +
> /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
> #define PRG_ETH0_CLK_M250_SEL_SHIFT 4
> #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
> @@ -47,12 +52,20 @@
>
> #define MUX_CLK_NUM_PARENTS 2
>
> +struct meson8b_dwmac;
> +
> +struct meson8b_dwmac_data {
> + int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
> +};
> +
> struct meson8b_dwmac {
> - struct device *dev;
> - void __iomem *regs;
> - phy_interface_t phy_mode;
> - struct clk *rgmii_tx_clk;
> - u32 tx_delay_ns;
> + struct device *dev;
> + void __iomem *regs;
> +
> + const struct meson8b_dwmac_data *data;
> + phy_interface_t phy_mode;
> + struct clk *rgmii_tx_clk;
> + u32 tx_delay_ns;
> };
>
> struct meson8b_dwmac_clk_configs {
> @@ -171,6 +184,59 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
> return 0;
> }
>
> +static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
> +{
> + switch (dwmac->phy_mode) {
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + /* enable RGMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_RGMII_MODE,
> + PRG_ETH0_RGMII_MODE);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + /* disable RGMII mode -> enables RMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_RGMII_MODE, 0);
> + break;
> + default:
> + dev_err(dwmac->dev, "fail to set phy-mode %s\n",
> + phy_modes(dwmac->phy_mode));
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
> +{
> + switch (dwmac->phy_mode) {
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + /* enable RGMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_EXT_PHY_MODE_MASK,
> + PRG_ETH0_EXT_RGMII_MODE);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + /* disable RGMII mode -> enables RMII mode */
if you have to re-send it for whatever reason:
maybe you could remove the comments from meson_axg_set_phy_mode. the
"older" register layout requires un-setting RGMII mode to enable RMII
mode. however, for AXG there seem to be two dedicated values (1 and 4)
for each mode
apart from that:
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_EXT_PHY_MODE_MASK,
> + PRG_ETH0_EXT_RMII_MODE);
> + break;
> + default:
> + dev_err(dwmac->dev, "fail to set phy-mode %s\n",
> + phy_modes(dwmac->phy_mode));
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
> {
> int ret;
> @@ -188,10 +254,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> - /* enable RGMII mode */
> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
> - PRG_ETH0_RGMII_MODE);
> -
> /* only relevant for RMII mode -> disable in RGMII mode */
> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> PRG_ETH0_INVERTED_RMII_CLK, 0);
> @@ -224,10 +286,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
> break;
>
> case PHY_INTERFACE_MODE_RMII:
> - /* disable RGMII mode -> enables RMII mode */
> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
> - 0);
> -
> /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> PRG_ETH0_INVERTED_RMII_CLK,
> @@ -274,6 +332,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> goto err_remove_config_dt;
> }
>
> + dwmac->data = (const struct meson8b_dwmac_data *)
> + of_device_get_match_data(&pdev->dev);
> + if (!dwmac->data)
> + return -EINVAL;
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(dwmac->regs)) {
> @@ -298,6 +361,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> if (ret)
> goto err_remove_config_dt;
>
> + ret = dwmac->data->set_phy_mode(dwmac);
> + if (ret)
> + goto err_remove_config_dt;
> +
> ret = meson8b_init_prg_eth(dwmac);
> if (ret)
> goto err_remove_config_dt;
> @@ -316,10 +383,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> return ret;
> }
>
> +static const struct meson8b_dwmac_data meson8b_dwmac_data = {
> + .set_phy_mode = meson8b_set_phy_mode,
> +};
> +
> +static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
> + .set_phy_mode = meson_axg_set_phy_mode,
> +};
> +
> static const struct of_device_id meson8b_dwmac_match[] = {
> - { .compatible = "amlogic,meson8b-dwmac" },
> - { .compatible = "amlogic,meson8m2-dwmac" },
> - { .compatible = "amlogic,meson-gxbb-dwmac" },
> + {
> + .compatible = "amlogic,meson8b-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson8m2-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson-gxbb-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson-axg-dwmac",
> + .data = &meson_axg_dwmac_data,
> + },
> { }
> };
> MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
> --
> 2.17.0
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 2/2] net: stmmac: dwmac-meson: extend phy mode setting
@ 2018-05-01 13:20 ` Martin Blumenstingl
0 siblings, 0 replies; 20+ messages in thread
From: Martin Blumenstingl @ 2018-05-01 13:20 UTC (permalink / raw)
To: linux-arm-kernel
Hello Yixun,
On Sat, Apr 28, 2018 at 12:21 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
> is extended from bit[0] to bit[2:0].
> There is no problem if we configure it to the RGMII 1000M PHY mode,
> since the register setting is coincidentally compatible with previous one,
> but for the RMII 100M PHY mode, the configuration need to be changed to
> value - b100.
> This patch was verified with a RTL8201F 100M ethernet PHY.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
> 1 file changed, 104 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> index 7cb794094a70..4ff231df7322 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> @@ -18,6 +18,7 @@
> #include <linux/io.h>
> #include <linux/ioport.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/of_net.h>
> #include <linux/mfd/syscon.h>
> #include <linux/platform_device.h>
> @@ -29,6 +30,10 @@
>
> #define PRG_ETH0_RGMII_MODE BIT(0)
>
> +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
> +#define PRG_ETH0_EXT_RGMII_MODE 1
> +#define PRG_ETH0_EXT_RMII_MODE 4
> +
> /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
> #define PRG_ETH0_CLK_M250_SEL_SHIFT 4
> #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
> @@ -47,12 +52,20 @@
>
> #define MUX_CLK_NUM_PARENTS 2
>
> +struct meson8b_dwmac;
> +
> +struct meson8b_dwmac_data {
> + int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
> +};
> +
> struct meson8b_dwmac {
> - struct device *dev;
> - void __iomem *regs;
> - phy_interface_t phy_mode;
> - struct clk *rgmii_tx_clk;
> - u32 tx_delay_ns;
> + struct device *dev;
> + void __iomem *regs;
> +
> + const struct meson8b_dwmac_data *data;
> + phy_interface_t phy_mode;
> + struct clk *rgmii_tx_clk;
> + u32 tx_delay_ns;
> };
>
> struct meson8b_dwmac_clk_configs {
> @@ -171,6 +184,59 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
> return 0;
> }
>
> +static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
> +{
> + switch (dwmac->phy_mode) {
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + /* enable RGMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_RGMII_MODE,
> + PRG_ETH0_RGMII_MODE);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + /* disable RGMII mode -> enables RMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_RGMII_MODE, 0);
> + break;
> + default:
> + dev_err(dwmac->dev, "fail to set phy-mode %s\n",
> + phy_modes(dwmac->phy_mode));
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
> +{
> + switch (dwmac->phy_mode) {
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + /* enable RGMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_EXT_PHY_MODE_MASK,
> + PRG_ETH0_EXT_RGMII_MODE);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + /* disable RGMII mode -> enables RMII mode */
if you have to re-send it for whatever reason:
maybe you could remove the comments from meson_axg_set_phy_mode. the
"older" register layout requires un-setting RGMII mode to enable RMII
mode. however, for AXG there seem to be two dedicated values (1 and 4)
for each mode
apart from that:
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_EXT_PHY_MODE_MASK,
> + PRG_ETH0_EXT_RMII_MODE);
> + break;
> + default:
> + dev_err(dwmac->dev, "fail to set phy-mode %s\n",
> + phy_modes(dwmac->phy_mode));
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
> {
> int ret;
> @@ -188,10 +254,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> - /* enable RGMII mode */
> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
> - PRG_ETH0_RGMII_MODE);
> -
> /* only relevant for RMII mode -> disable in RGMII mode */
> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> PRG_ETH0_INVERTED_RMII_CLK, 0);
> @@ -224,10 +286,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
> break;
>
> case PHY_INTERFACE_MODE_RMII:
> - /* disable RGMII mode -> enables RMII mode */
> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
> - 0);
> -
> /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> PRG_ETH0_INVERTED_RMII_CLK,
> @@ -274,6 +332,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> goto err_remove_config_dt;
> }
>
> + dwmac->data = (const struct meson8b_dwmac_data *)
> + of_device_get_match_data(&pdev->dev);
> + if (!dwmac->data)
> + return -EINVAL;
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(dwmac->regs)) {
> @@ -298,6 +361,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> if (ret)
> goto err_remove_config_dt;
>
> + ret = dwmac->data->set_phy_mode(dwmac);
> + if (ret)
> + goto err_remove_config_dt;
> +
> ret = meson8b_init_prg_eth(dwmac);
> if (ret)
> goto err_remove_config_dt;
> @@ -316,10 +383,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> return ret;
> }
>
> +static const struct meson8b_dwmac_data meson8b_dwmac_data = {
> + .set_phy_mode = meson8b_set_phy_mode,
> +};
> +
> +static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
> + .set_phy_mode = meson_axg_set_phy_mode,
> +};
> +
> static const struct of_device_id meson8b_dwmac_match[] = {
> - { .compatible = "amlogic,meson8b-dwmac" },
> - { .compatible = "amlogic,meson8m2-dwmac" },
> - { .compatible = "amlogic,meson-gxbb-dwmac" },
> + {
> + .compatible = "amlogic,meson8b-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson8m2-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson-gxbb-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson-axg-dwmac",
> + .data = &meson_axg_dwmac_data,
> + },
> { }
> };
> MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
> --
> 2.17.0
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 2/2] net: stmmac: dwmac-meson: extend phy mode setting
@ 2018-05-01 13:20 ` Martin Blumenstingl
0 siblings, 0 replies; 20+ messages in thread
From: Martin Blumenstingl @ 2018-05-01 13:20 UTC (permalink / raw)
To: linus-amlogic
Hello Yixun,
On Sat, Apr 28, 2018 at 12:21 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
> is extended from bit[0] to bit[2:0].
> There is no problem if we configure it to the RGMII 1000M PHY mode,
> since the register setting is coincidentally compatible with previous one,
> but for the RMII 100M PHY mode, the configuration need to be changed to
> value - b100.
> This patch was verified with a RTL8201F 100M ethernet PHY.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++++++++++++++---
> 1 file changed, 104 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> index 7cb794094a70..4ff231df7322 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> @@ -18,6 +18,7 @@
> #include <linux/io.h>
> #include <linux/ioport.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/of_net.h>
> #include <linux/mfd/syscon.h>
> #include <linux/platform_device.h>
> @@ -29,6 +30,10 @@
>
> #define PRG_ETH0_RGMII_MODE BIT(0)
>
> +#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
> +#define PRG_ETH0_EXT_RGMII_MODE 1
> +#define PRG_ETH0_EXT_RMII_MODE 4
> +
> /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
> #define PRG_ETH0_CLK_M250_SEL_SHIFT 4
> #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
> @@ -47,12 +52,20 @@
>
> #define MUX_CLK_NUM_PARENTS 2
>
> +struct meson8b_dwmac;
> +
> +struct meson8b_dwmac_data {
> + int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
> +};
> +
> struct meson8b_dwmac {
> - struct device *dev;
> - void __iomem *regs;
> - phy_interface_t phy_mode;
> - struct clk *rgmii_tx_clk;
> - u32 tx_delay_ns;
> + struct device *dev;
> + void __iomem *regs;
> +
> + const struct meson8b_dwmac_data *data;
> + phy_interface_t phy_mode;
> + struct clk *rgmii_tx_clk;
> + u32 tx_delay_ns;
> };
>
> struct meson8b_dwmac_clk_configs {
> @@ -171,6 +184,59 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
> return 0;
> }
>
> +static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
> +{
> + switch (dwmac->phy_mode) {
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + /* enable RGMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_RGMII_MODE,
> + PRG_ETH0_RGMII_MODE);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + /* disable RGMII mode -> enables RMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_RGMII_MODE, 0);
> + break;
> + default:
> + dev_err(dwmac->dev, "fail to set phy-mode %s\n",
> + phy_modes(dwmac->phy_mode));
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
> +{
> + switch (dwmac->phy_mode) {
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + /* enable RGMII mode */
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_EXT_PHY_MODE_MASK,
> + PRG_ETH0_EXT_RGMII_MODE);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + /* disable RGMII mode -> enables RMII mode */
if you have to re-send it for whatever reason:
maybe you could remove the comments from meson_axg_set_phy_mode. the
"older" register layout requires un-setting RGMII mode to enable RMII
mode. however, for AXG there seem to be two dedicated values (1 and 4)
for each mode
apart from that:
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> + PRG_ETH0_EXT_PHY_MODE_MASK,
> + PRG_ETH0_EXT_RMII_MODE);
> + break;
> + default:
> + dev_err(dwmac->dev, "fail to set phy-mode %s\n",
> + phy_modes(dwmac->phy_mode));
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
> {
> int ret;
> @@ -188,10 +254,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> - /* enable RGMII mode */
> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
> - PRG_ETH0_RGMII_MODE);
> -
> /* only relevant for RMII mode -> disable in RGMII mode */
> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> PRG_ETH0_INVERTED_RMII_CLK, 0);
> @@ -224,10 +286,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
> break;
>
> case PHY_INTERFACE_MODE_RMII:
> - /* disable RGMII mode -> enables RMII mode */
> - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
> - 0);
> -
> /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
> meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> PRG_ETH0_INVERTED_RMII_CLK,
> @@ -274,6 +332,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> goto err_remove_config_dt;
> }
>
> + dwmac->data = (const struct meson8b_dwmac_data *)
> + of_device_get_match_data(&pdev->dev);
> + if (!dwmac->data)
> + return -EINVAL;
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(dwmac->regs)) {
> @@ -298,6 +361,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> if (ret)
> goto err_remove_config_dt;
>
> + ret = dwmac->data->set_phy_mode(dwmac);
> + if (ret)
> + goto err_remove_config_dt;
> +
> ret = meson8b_init_prg_eth(dwmac);
> if (ret)
> goto err_remove_config_dt;
> @@ -316,10 +383,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
> return ret;
> }
>
> +static const struct meson8b_dwmac_data meson8b_dwmac_data = {
> + .set_phy_mode = meson8b_set_phy_mode,
> +};
> +
> +static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
> + .set_phy_mode = meson_axg_set_phy_mode,
> +};
> +
> static const struct of_device_id meson8b_dwmac_match[] = {
> - { .compatible = "amlogic,meson8b-dwmac" },
> - { .compatible = "amlogic,meson8m2-dwmac" },
> - { .compatible = "amlogic,meson-gxbb-dwmac" },
> + {
> + .compatible = "amlogic,meson8b-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson8m2-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson-gxbb-dwmac",
> + .data = &meson8b_dwmac_data,
> + },
> + {
> + .compatible = "amlogic,meson-axg-dwmac",
> + .data = &meson_axg_dwmac_data,
> + },
> { }
> };
> MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
> --
> 2.17.0
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC
2018-04-28 10:21 ` Yixun Lan
(?)
@ 2018-05-01 15:30 ` David Miller
-1 siblings, 0 replies; 20+ messages in thread
From: David Miller @ 2018-05-01 15:30 UTC (permalink / raw)
To: yixun.lan
Cc: netdev, khilman, carlo, robh, jbrunet, martin.blumenstingl,
linux-amlogic, linux-arm-kernel, linux-kernel, devicetree
From: Yixun Lan <yixun.lan@amlogic.com>
Date: Sat, 28 Apr 2018 10:21:09 +0000
> Due to the dwmac glue layer register changed, we need to
> introduce a new compatible name for the Meson-AXG SoC
> to support for the RMII 100M ethernet PHY.
>
> Change since v1 at [1]:
> - implement set_phy_mode() for each SoC
>
> [1] https://lkml.kernel.org/r/20180426160508.29380-1-yixun.lan@amlogic.com
Series applied, thank you.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC
@ 2018-05-01 15:30 ` David Miller
0 siblings, 0 replies; 20+ messages in thread
From: David Miller @ 2018-05-01 15:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Yixun Lan <yixun.lan@amlogic.com>
Date: Sat, 28 Apr 2018 10:21:09 +0000
> Due to the dwmac glue layer register changed, we need to
> introduce a new compatible name for the Meson-AXG SoC
> to support for the RMII 100M ethernet PHY.
>
> Change since v1 at [1]:
> - implement set_phy_mode() for each SoC
>
> [1] https://lkml.kernel.org/r/20180426160508.29380-1-yixun.lan at amlogic.com
Series applied, thank you.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC
@ 2018-05-01 15:30 ` David Miller
0 siblings, 0 replies; 20+ messages in thread
From: David Miller @ 2018-05-01 15:30 UTC (permalink / raw)
To: linus-amlogic
From: Yixun Lan <yixun.lan@amlogic.com>
Date: Sat, 28 Apr 2018 10:21:09 +0000
> Due to the dwmac glue layer register changed, we need to
> introduce a new compatible name for the Meson-AXG SoC
> to support for the RMII 100M ethernet PHY.
>
> Change since v1 at [1]:
> - implement set_phy_mode() for each SoC
>
> [1] https://lkml.kernel.org/r/20180426160508.29380-1-yixun.lan at amlogic.com
Series applied, thank you.
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2018-05-01 15:30 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-28 10:21 [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC Yixun Lan
2018-04-28 10:21 ` Yixun Lan
2018-04-28 10:21 ` Yixun Lan
2018-04-28 10:21 ` Yixun Lan
2018-04-28 10:21 ` [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name " Yixun Lan
2018-04-28 10:21 ` Yixun Lan
2018-04-28 10:21 ` Yixun Lan
2018-04-28 10:21 ` Yixun Lan
2018-05-01 12:55 ` Rob Herring
2018-05-01 12:55 ` Rob Herring
2018-05-01 12:55 ` Rob Herring
2018-04-28 10:21 ` [PATCH v2 2/2] net: stmmac: dwmac-meson: extend phy mode setting Yixun Lan
2018-04-28 10:21 ` Yixun Lan
2018-04-28 10:21 ` Yixun Lan
2018-05-01 13:20 ` Martin Blumenstingl
2018-05-01 13:20 ` Martin Blumenstingl
2018-05-01 13:20 ` Martin Blumenstingl
2018-05-01 15:30 ` [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG SoC David Miller
2018-05-01 15:30 ` David Miller
2018-05-01 15:30 ` David Miller
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.