All of lore.kernel.org
 help / color / mirror / Atom feed
From: Vasily Khoruzhick <anarsoul@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 1/2] pwm: sunxi: add support for PWM found on Allwinner A64
Date: Sat, 28 Apr 2018 14:05:14 -0700	[thread overview]
Message-ID: <20180428210515.12993-2-anarsoul@gmail.com> (raw)
In-Reply-To: <20180428210515.12993-1-anarsoul@gmail.com>

This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
 arch/arm/include/asm/arch-sunxi/gpio.h |   1 +
 arch/arm/include/asm/arch-sunxi/pwm.h  |  12 ++
 drivers/pwm/Kconfig                    |   7 +
 drivers/pwm/Makefile                   |   1 +
 drivers/pwm/sunxi_pwm.c                | 178 +++++++++++++++++++++++++
 5 files changed, 199 insertions(+)
 create mode 100644 drivers/pwm/sunxi_pwm.c

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 24f85206c8..7265d18099 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -173,6 +173,7 @@ enum sunxi_gpio_number {
 #define SUN8I_GPD_SDC1		3
 #define SUNXI_GPD_LCD0		2
 #define SUNXI_GPD_LVDS0		3
+#define SUNXI_GPD_PWM		2
 
 #define SUN5I_GPE_SDC2		3
 #define SUN8I_GPE_TWI2		3
diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h
index 5884b5dbe7..e9368f2fb8 100644
--- a/arch/arm/include/asm/arch-sunxi/pwm.h
+++ b/arch/arm/include/asm/arch-sunxi/pwm.h
@@ -11,8 +11,15 @@
 #define SUNXI_PWM_CH0_PERIOD		(SUNXI_PWM_BASE + 4)
 
 #define SUNXI_PWM_CTRL_PRESCALE0(x)	((x) & 0xf)
+#define SUNXI_PWM_CTRL_PRESCALE0_MASK	0xf
 #define SUNXI_PWM_CTRL_ENABLE0		(0x5 << 4)
 #define SUNXI_PWM_CTRL_POLARITY0(x)	((x) << 5)
+#define SUNXI_PWM_CTRL_CH0_ACT_STA	BIT(5)
+#define SUNXI_PWM_CTRL_CLK_GATE		BIT(6)
+
+#define SUNXI_PWM_CH0_PERIOD_MAX	(0xffff)
+#define SUNXI_PWM_CH0_PERIOD_PRD(x)	((x & 0xffff) << 16)
+#define SUNXI_PWM_CH0_PERIOD_DUTY(x)	((x) & 0xffff)
 
 #define SUNXI_PWM_PERIOD_80PCT		0x04af03c0
 
@@ -31,4 +38,9 @@
 #define SUNXI_PWM_MUX			SUN8I_GPH_PWM
 #endif
 
+struct sunxi_pwm {
+	u32 ctrl;
+	u32 ch0_period;
+};
+
 #endif
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e827558052..2984b79766 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -43,3 +43,10 @@ config PWM_TEGRA
 	  four channels with a programmable period and duty cycle. Only a
 	  32KHz clock is supported by the driver but the duty cycle is
 	  configurable.
+
+config PWM_SUNXI
+	bool "Enable support for the Allwinner Sunxi PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on H3, A64 and other Allwinner SoCs. It supports a
+	  programmable period and duty cycle. A 16-bit counter is used.
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 29d59916cb..1a8f8a58bc 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PWM_IMX)		+= pwm-imx.o pwm-imx-util.o
 obj-$(CONFIG_PWM_ROCKCHIP)	+= rk_pwm.o
 obj-$(CONFIG_PWM_SANDBOX)	+= sandbox_pwm.o
 obj-$(CONFIG_PWM_TEGRA)		+= tegra_pwm.o
+obj-$(CONFIG_PWM_SUNXI)		+= sunxi_pwm.o
diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c
new file mode 100644
index 0000000000..8e7ba347a7
--- /dev/null
+++ b/drivers/pwm/sunxi_pwm.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <pwm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/gpio.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OSC_24MHZ 24000000
+
+struct sunxi_pwm_priv {
+	struct sunxi_pwm *regs;
+	bool invert;
+	u32 prescaler;
+};
+
+static const u32 prescaler_table[] = {
+	120,	/* 0000 */
+	180,	/* 0001 */
+	240,	/* 0010 */
+	360,	/* 0011 */
+	480,	/* 0100 */
+	0,	/* 0101 */
+	0,	/* 0110 */
+	0,	/* 0111 */
+	12000,	/* 1000 */
+	24000,	/* 1001 */
+	36000,	/* 1010 */
+	48000,	/* 1011 */
+	72000,	/* 1100 */
+	0,	/* 1101 */
+	0,	/* 1110 */
+	1,	/* 1111 */
+};
+
+static int sunxi_pwm_config_pinmux(void)
+{
+#ifdef CONFIG_MACH_SUN50I
+	sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
+#endif
+	return 0;
+}
+
+static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
+				bool polarity)
+{
+	struct sunxi_pwm_priv *priv = dev_get_priv(dev);
+
+	debug("%s: polarity=%u\n", __func__, polarity);
+	priv->invert = polarity;
+
+	return 0;
+}
+
+static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
+				uint period_ns, uint duty_ns)
+{
+	struct sunxi_pwm_priv *priv = dev_get_priv(dev);
+	struct sunxi_pwm *regs = priv->regs;
+	int prescaler;
+	u32 v, period = 0, duty;
+	u64 scaled_freq = 0;
+	const u32 nsecs_per_sec = 1000000000U;
+
+	debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
+
+	for (prescaler = 0; prescaler < SUNXI_PWM_CTRL_PRESCALE0_MASK;
+	     prescaler++) {
+		if (!prescaler_table[prescaler])
+			continue;
+		scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
+		period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
+		if (period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX)
+			break;
+	}
+
+	if (period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
+		debug("%s: failed to find prescaler value\n", __func__);
+		return -EINVAL;
+	}
+
+	duty = lldiv(scaled_freq * duty_ns, nsecs_per_sec);
+
+	if (priv->prescaler != prescaler) {
+		/* Mask clock to update prescaler */
+		v = readl(&regs->ctrl);
+		v &= ~SUNXI_PWM_CTRL_CLK_GATE;
+		writel(v, &regs->ctrl);
+		v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
+		v |= (priv->prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
+		writel(v, &regs->ctrl);
+		v |= SUNXI_PWM_CTRL_CLK_GATE;
+		writel(v, &regs->ctrl);
+		priv->prescaler = prescaler;
+	}
+
+	writel(SUNXI_PWM_CH0_PERIOD_PRD(period) |
+	       SUNXI_PWM_CH0_PERIOD_DUTY(duty), &regs->ch0_period);
+
+	debug("%s: prescaler: %d, period: %d, duty: %d\n",
+	      __func__, priv->prescaler,
+	      period, duty);
+
+	return 0;
+}
+
+static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+	struct sunxi_pwm_priv *priv = dev_get_priv(dev);
+	struct sunxi_pwm *regs = priv->regs;
+	u32 v;
+
+	debug("%s: Enable '%s'\n", __func__, dev->name);
+
+	v = readl(&regs->ctrl);
+	if (!enable) {
+		v &= ~SUNXI_PWM_CTRL_ENABLE0;
+		writel(v, &regs->ctrl);
+		return 0;
+	}
+
+	sunxi_pwm_config_pinmux();
+
+	if (priv->invert)
+		v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
+	else
+		v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
+	v |= SUNXI_PWM_CTRL_ENABLE0;
+	writel(v, &regs->ctrl);
+
+	return 0;
+}
+
+static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sunxi_pwm_priv *priv = dev_get_priv(dev);
+
+	priv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);
+
+	return 0;
+}
+
+static int sunxi_pwm_probe(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct pwm_ops sunxi_pwm_ops = {
+	.set_invert	= sunxi_pwm_set_invert,
+	.set_config	= sunxi_pwm_set_config,
+	.set_enable	= sunxi_pwm_set_enable,
+};
+
+static const struct udevice_id sunxi_pwm_ids[] = {
+	{ .compatible = "allwinner,sun50i-a64-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(sunxi_pwm) = {
+	.name	= "sunxi_pwm",
+	.id	= UCLASS_PWM,
+	.of_match = sunxi_pwm_ids,
+	.ops	= &sunxi_pwm_ops,
+	.ofdata_to_platdata	= sunxi_pwm_ofdata_to_platdata,
+	.probe		= sunxi_pwm_probe,
+	.priv_auto_alloc_size	= sizeof(struct sunxi_pwm_priv),
+};
-- 
2.17.0

  reply	other threads:[~2018-04-28 21:05 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-28 21:05 [U-Boot] [PATCH v3 0/2] sunxi: add PWM driver for A64 Vasily Khoruzhick
2018-04-28 21:05 ` Vasily Khoruzhick [this message]
2018-05-02  9:24   ` [U-Boot] [PATCH v3 1/2] pwm: sunxi: add support for PWM found on Allwinner A64 Maxime Ripard
2018-05-02 12:42     ` Anatolij Gustschin
2018-04-28 21:05 ` [U-Boot] [PATCH v3 2/2] dts: sunxi: add PWM node for sun50i Vasily Khoruzhick

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180428210515.12993-2-anarsoul@gmail.com \
    --to=anarsoul@gmail.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.