From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-wm0-f65.google.com ([74.125.82.65]:34486 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753973AbeD3PfG (ORCPT ); Mon, 30 Apr 2018 11:35:06 -0400 Received: by mail-wm0-f65.google.com with SMTP id a137so10498482wme.1 for ; Mon, 30 Apr 2018 08:35:05 -0700 (PDT) Date: Mon, 30 Apr 2018 17:35:02 +0200 From: Daniel Vetter To: Christian =?iso-8859-1?Q?K=F6nig?= Cc: Daniel Vetter , DRI Development , Intel Graphics Development , Daniel Vetter , Sumit Semwal , Gustavo Padovan , linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, Alex Deucher Subject: Re: [PATCH 04/17] dma-fence: Allow wait_any_timeout for all fences Message-ID: <20180430153502.GQ12521@phenom.ffwll.local> References: <20180427061724.28497-1-daniel.vetter@ffwll.ch> <20180427061724.28497-5-daniel.vetter@ffwll.ch> <1df9beec-8ee4-5740-954a-a2a5dbc4fd03@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1df9beec-8ee4-5740-954a-a2a5dbc4fd03@amd.com> Sender: linux-media-owner@vger.kernel.org List-ID: On Sun, Apr 29, 2018 at 09:11:31AM +0200, Christian König wrote: > Am 27.04.2018 um 08:17 schrieb Daniel Vetter: > > When this was introduced in > > > > commit a519435a96597d8cd96123246fea4ae5a6c90b02 > > Author: Christian König > > Date: Tue Oct 20 16:34:16 2015 +0200 > > > > dma-buf/fence: add fence_wait_any_timeout function v2 > > > > there was a restriction added that this only works if the dma-fence > > uses the dma_fence_default_wait hook. Which works for amdgpu, which is > > the only caller. Well, until you share some buffers with e.g. i915, > > then you get an -EINVAL. > > > > But there's really no reason for this, because all drivers must > > support callbacks. The special ->wait hook is only as an optimization; > > if the driver needs to create a worker thread for an active callback, > > then it can avoid to do that if it knows that there's a process > > context available already. So ->wait is just an optimization, just > > using the logic in dma_fence_default_wait() should work for all > > drivers. > > > > Let's remove this restriction. > > Mhm, that was intentional introduced because for radeon that is not only an > optimization, but mandatory for correct operation. > > On the other hand radeon isn't using this function, so it should be fine as > long as the Intel driver can live with it. Well dma-buf already requires that dma_fence_add_callback works correctly. And so do various users of it as soon as you engage in a bit of buffer sharing. I guess whomever cares about buffer sharing with radeon gets to fix this (you need to spawn a kthread or whatever in ->enable_signaling which does the same work as your optimized ->wait callback). But yeah, I'm definitely not making things work with this series, just a bit more obvious that there's a problem already. -Daniel > > Christian. > > > > > Signed-off-by: Daniel Vetter > > Cc: Sumit Semwal > > Cc: Gustavo Padovan > > Cc: linux-media@vger.kernel.org > > Cc: linaro-mm-sig@lists.linaro.org > > Cc: Christian König > > Cc: Alex Deucher > > --- > > drivers/dma-buf/dma-fence.c | 5 ----- > > 1 file changed, 5 deletions(-) > > > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > > index 7b5b40d6b70e..59049375bd19 100644 > > --- a/drivers/dma-buf/dma-fence.c > > +++ b/drivers/dma-buf/dma-fence.c > > @@ -503,11 +503,6 @@ dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, > > for (i = 0; i < count; ++i) { > > struct dma_fence *fence = fences[i]; > > - if (fence->ops->wait != dma_fence_default_wait) { > > - ret = -EINVAL; > > - goto fence_rm_cb; > > - } > > - > > cb[i].task = current; > > if (dma_fence_add_callback(fence, &cb[i].base, > > dma_fence_default_wait_cb)) { > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 04/17] dma-fence: Allow wait_any_timeout for all fences Date: Mon, 30 Apr 2018 17:35:02 +0200 Message-ID: <20180430153502.GQ12521@phenom.ffwll.local> References: <20180427061724.28497-1-daniel.vetter@ffwll.ch> <20180427061724.28497-5-daniel.vetter@ffwll.ch> <1df9beec-8ee4-5740-954a-a2a5dbc4fd03@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1df9beec-8ee4-5740-954a-a2a5dbc4fd03@amd.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Christian =?iso-8859-1?Q?K=F6nig?= Cc: Intel Graphics Development , DRI Development , linaro-mm-sig@lists.linaro.org, Daniel Vetter , Alex Deucher , Daniel Vetter , Sumit Semwal , linux-media@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org T24gU3VuLCBBcHIgMjksIDIwMTggYXQgMDk6MTE6MzFBTSArMDIwMCwgQ2hyaXN0aWFuIEvDtm5p ZyB3cm90ZToKPiBBbSAyNy4wNC4yMDE4IHVtIDA4OjE3IHNjaHJpZWIgRGFuaWVsIFZldHRlcjoK PiA+IFdoZW4gdGhpcyB3YXMgaW50cm9kdWNlZCBpbgo+ID4gCj4gPiBjb21taXQgYTUxOTQzNWE5 NjU5N2Q4Y2Q5NjEyMzI0NmZlYTRhZTVhNmM5MGIwMgo+ID4gQXV0aG9yOiBDaHJpc3RpYW4gS8O2 bmlnIDxjaHJpc3RpYW4ua29lbmlnQGFtZC5jb20+Cj4gPiBEYXRlOiAgIFR1ZSBPY3QgMjAgMTY6 MzQ6MTYgMjAxNSArMDIwMAo+ID4gCj4gPiAgICAgIGRtYS1idWYvZmVuY2U6IGFkZCBmZW5jZV93 YWl0X2FueV90aW1lb3V0IGZ1bmN0aW9uIHYyCj4gPiAKPiA+IHRoZXJlIHdhcyBhIHJlc3RyaWN0 aW9uIGFkZGVkIHRoYXQgdGhpcyBvbmx5IHdvcmtzIGlmIHRoZSBkbWEtZmVuY2UKPiA+IHVzZXMg dGhlIGRtYV9mZW5jZV9kZWZhdWx0X3dhaXQgaG9vay4gV2hpY2ggd29ya3MgZm9yIGFtZGdwdSwg d2hpY2ggaXMKPiA+IHRoZSBvbmx5IGNhbGxlci4gV2VsbCwgdW50aWwgeW91IHNoYXJlIHNvbWUg YnVmZmVycyB3aXRoIGUuZy4gaTkxNSwKPiA+IHRoZW4geW91IGdldCBhbiAtRUlOVkFMLgo+ID4g Cj4gPiBCdXQgdGhlcmUncyByZWFsbHkgbm8gcmVhc29uIGZvciB0aGlzLCBiZWNhdXNlIGFsbCBk cml2ZXJzIG11c3QKPiA+IHN1cHBvcnQgY2FsbGJhY2tzLiBUaGUgc3BlY2lhbCAtPndhaXQgaG9v ayBpcyBvbmx5IGFzIGFuIG9wdGltaXphdGlvbjsKPiA+IGlmIHRoZSBkcml2ZXIgbmVlZHMgdG8g Y3JlYXRlIGEgd29ya2VyIHRocmVhZCBmb3IgYW4gYWN0aXZlIGNhbGxiYWNrLAo+ID4gdGhlbiBp dCBjYW4gYXZvaWQgdG8gZG8gdGhhdCBpZiBpdCBrbm93cyB0aGF0IHRoZXJlJ3MgYSBwcm9jZXNz Cj4gPiBjb250ZXh0IGF2YWlsYWJsZSBhbHJlYWR5LiBTbyAtPndhaXQgaXMganVzdCBhbiBvcHRp bWl6YXRpb24sIGp1c3QKPiA+IHVzaW5nIHRoZSBsb2dpYyBpbiBkbWFfZmVuY2VfZGVmYXVsdF93 YWl0KCkgc2hvdWxkIHdvcmsgZm9yIGFsbAo+ID4gZHJpdmVycy4KPiA+IAo+ID4gTGV0J3MgcmVt b3ZlIHRoaXMgcmVzdHJpY3Rpb24uCj4gCj4gTWhtLCB0aGF0IHdhcyBpbnRlbnRpb25hbCBpbnRy b2R1Y2VkIGJlY2F1c2UgZm9yIHJhZGVvbiB0aGF0IGlzIG5vdCBvbmx5IGFuCj4gb3B0aW1pemF0 aW9uLCBidXQgbWFuZGF0b3J5IGZvciBjb3JyZWN0IG9wZXJhdGlvbi4KPiAKPiBPbiB0aGUgb3Ro ZXIgaGFuZCByYWRlb24gaXNuJ3QgdXNpbmcgdGhpcyBmdW5jdGlvbiwgc28gaXQgc2hvdWxkIGJl IGZpbmUgYXMKPiBsb25nIGFzIHRoZSBJbnRlbCBkcml2ZXIgY2FuIGxpdmUgd2l0aCBpdC4KCldl bGwgZG1hLWJ1ZiBhbHJlYWR5IHJlcXVpcmVzIHRoYXQgZG1hX2ZlbmNlX2FkZF9jYWxsYmFjayB3 b3JrcyBjb3JyZWN0bHkuCkFuZCBzbyBkbyB2YXJpb3VzIHVzZXJzIG9mIGl0IGFzIHNvb24gYXMg eW91IGVuZ2FnZSBpbiBhIGJpdCBvZiBidWZmZXIKc2hhcmluZy4gSSBndWVzcyB3aG9tZXZlciBj YXJlcyBhYm91dCBidWZmZXIgc2hhcmluZyB3aXRoIHJhZGVvbiBnZXRzIHRvCmZpeCB0aGlzICh5 b3UgbmVlZCB0byBzcGF3biBhIGt0aHJlYWQgb3Igd2hhdGV2ZXIgaW4gLT5lbmFibGVfc2lnbmFs aW5nCndoaWNoIGRvZXMgdGhlIHNhbWUgd29yayBhcyB5b3VyIG9wdGltaXplZCAtPndhaXQgY2Fs bGJhY2spLgoKQnV0IHllYWgsIEknbSBkZWZpbml0ZWx5IG5vdCBtYWtpbmcgdGhpbmdzIHdvcmsg d2l0aCB0aGlzIHNlcmllcywganVzdCBhCmJpdCBtb3JlIG9idmlvdXMgdGhhdCB0aGVyZSdzIGEg cHJvYmxlbSBhbHJlYWR5LgotRGFuaWVsCgo+IAo+IENocmlzdGlhbi4KPiAKPiA+IAo+ID4gU2ln bmVkLW9mZi1ieTogRGFuaWVsIFZldHRlciA8ZGFuaWVsLnZldHRlckBpbnRlbC5jb20+Cj4gPiBD YzogU3VtaXQgU2Vtd2FsIDxzdW1pdC5zZW13YWxAbGluYXJvLm9yZz4KPiA+IENjOiBHdXN0YXZv IFBhZG92YW4gPGd1c3Rhdm9AcGFkb3Zhbi5vcmc+Cj4gPiBDYzogbGludXgtbWVkaWFAdmdlci5r ZXJuZWwub3JnCj4gPiBDYzogbGluYXJvLW1tLXNpZ0BsaXN0cy5saW5hcm8ub3JnCj4gPiBDYzog Q2hyaXN0aWFuIEvDtm5pZyA8Y2hyaXN0aWFuLmtvZW5pZ0BhbWQuY29tPgo+ID4gQ2M6IEFsZXgg RGV1Y2hlciA8YWxleGFuZGVyLmRldWNoZXJAYW1kLmNvbT4KPiA+IC0tLQo+ID4gICBkcml2ZXJz L2RtYS1idWYvZG1hLWZlbmNlLmMgfCA1IC0tLS0tCj4gPiAgIDEgZmlsZSBjaGFuZ2VkLCA1IGRl bGV0aW9ucygtKQo+ID4gCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9kbWEtYnVmL2RtYS1mZW5j ZS5jIGIvZHJpdmVycy9kbWEtYnVmL2RtYS1mZW5jZS5jCj4gPiBpbmRleCA3YjViNDBkNmI3MGUu LjU5MDQ5Mzc1YmQxOSAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvZG1hLWJ1Zi9kbWEtZmVuY2Uu Ywo+ID4gKysrIGIvZHJpdmVycy9kbWEtYnVmL2RtYS1mZW5jZS5jCj4gPiBAQCAtNTAzLDExICs1 MDMsNiBAQCBkbWFfZmVuY2Vfd2FpdF9hbnlfdGltZW91dChzdHJ1Y3QgZG1hX2ZlbmNlICoqZmVu Y2VzLCB1aW50MzJfdCBjb3VudCwKPiA+ICAgCWZvciAoaSA9IDA7IGkgPCBjb3VudDsgKytpKSB7 Cj4gPiAgIAkJc3RydWN0IGRtYV9mZW5jZSAqZmVuY2UgPSBmZW5jZXNbaV07Cj4gPiAtCQlpZiAo ZmVuY2UtPm9wcy0+d2FpdCAhPSBkbWFfZmVuY2VfZGVmYXVsdF93YWl0KSB7Cj4gPiAtCQkJcmV0 ID0gLUVJTlZBTDsKPiA+IC0JCQlnb3RvIGZlbmNlX3JtX2NiOwo+ID4gLQkJfQo+ID4gLQo+ID4g ICAJCWNiW2ldLnRhc2sgPSBjdXJyZW50Owo+ID4gICAJCWlmIChkbWFfZmVuY2VfYWRkX2NhbGxi YWNrKGZlbmNlLCAmY2JbaV0uYmFzZSwKPiA+ICAgCQkJCQkgICBkbWFfZmVuY2VfZGVmYXVsdF93 YWl0X2NiKSkgewo+IAoKLS0gCkRhbmllbCBWZXR0ZXIKU29mdHdhcmUgRW5naW5lZXIsIEludGVs IENvcnBvcmF0aW9uCmh0dHA6Ly9ibG9nLmZmd2xsLmNoCl9fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4 QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWls bWFuL2xpc3RpbmZvL2ludGVsLWdmeAo=