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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [patch V7 14/15] SBB 14
Date: Mon, 30 Apr 2018 11:49:32 -0400	[thread overview]
Message-ID: <20180430154932.GE3369@char.us.oracle.com> (raw)
In-Reply-To: <alpine.DEB.2.21.1804300753460.1595@nanos.tec.linutronix.de>

On Mon, Apr 30, 2018 at 07:57:19AM +0200, speck for Thomas Gleixner wrote:
> On Sun, 29 Apr 2018, speck for Konrad Rzeszutek Wilk wrote:
> > > +extern u64 x86_spec_ctrl_base;
> > > +
> > > +static inline u64 rds_tif_to_spec_ctrl(u64 tifn)
> > > +{
> > > +	BUILD_BUG_ON(TIF_RDS < SPEC_CTRL_RDS_SHIFT);
> > > +	return (tifn & _TIF_RDS) >> (TIF_RDS - SPEC_CTRL_RDS_SHIFT);
> > 
> > If my math is correct, the right side value is 3, not 2. That is
> > TIF_RDS (5) - SPEC_CTRL_RDS_SHIFT(2) = 3.
> > 
> > Then if _TIF_RDS is set we do:
> > 	1 >> 3
> 
> _TIF_RDS == (1 << TIF_RDS) == 0x20
> 
> Ergo if set:
> 
> 	0x20 >> 3 = 0x04
> 
> if not set:
> 
>        0x00 >> 3 = 0x00
> 
> Right?

<blushes> Yes. I missed the '_'.

With that explanation and the thing below, please add

Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

  reply	other threads:[~2018-04-30 15:49 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-29 19:30 [patch V7 00/15] SBB 0 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 01/15] SBB 1 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 02/15] SBB 2 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 03/15] SBB 3 Thomas Gleixner
2018-04-29 23:31   ` [MODERATED] " Linus Torvalds
2018-04-30  2:50     ` Konrad Rzeszutek Wilk
2018-04-30  7:09     ` David Woodhouse
2018-04-29 19:30 ` [patch V7 04/15] SBB 4 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 05/15] SBB 5 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 06/15] SBB 6 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 07/15] SBB 7 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 08/15] SBB 8 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 09/15] SBB 9 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 10/15] SBB 10 Thomas Gleixner
2018-04-30  0:16   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30  7:49     ` Thomas Gleixner
2018-04-29 19:30 ` [patch V7 11/15] SBB 11 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 12/15] SBB 12 Thomas Gleixner
2018-04-30  1:33   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-29 19:30 ` [patch V7 13/15] SBB 13 Thomas Gleixner
2018-04-30  1:48   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30  2:39     ` Konrad Rzeszutek Wilk
2018-04-30  3:17     ` Jon Masters
2018-04-30  8:35       ` Thomas Gleixner
2018-04-30  2:20   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30  2:36   ` Konrad Rzeszutek Wilk
2018-04-30 17:28   ` Konrad Rzeszutek Wilk
2018-04-29 19:30 ` [patch V7 14/15] SBB 14 Thomas Gleixner
2018-04-30  2:14   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30  5:57     ` Thomas Gleixner
2018-04-30 15:49       ` Konrad Rzeszutek Wilk [this message]
2018-04-29 19:31 ` [patch V7 15/15] SBB 15 Thomas Gleixner
2018-04-30  2:32   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30 15:56   ` Konrad Rzeszutek Wilk
2018-04-30 16:07     ` Thomas Gleixner
2018-04-30 19:30   ` [MODERATED] " Tim Chen
2018-04-30 19:36     ` Thomas Gleixner
2018-04-30 20:12       ` [MODERATED] " Tim Chen
2018-04-30 20:20         ` Konrad Rzeszutek Wilk
2018-04-30 20:44           ` Tim Chen
2018-04-30 20:28         ` Thomas Gleixner
2018-04-30 20:09     ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-29 20:14 ` [patch V7 00/15] SBB 0 Thomas Gleixner
2018-04-29 20:35 ` [MODERATED] " Borislav Petkov
2018-04-29 20:46   ` Konrad Rzeszutek Wilk
2018-04-29 20:57     ` Thomas Gleixner
2018-04-29 21:40     ` [MODERATED] " Borislav Petkov
2018-04-29 20:55   ` Thomas Gleixner
2018-04-29 22:05     ` Thomas Gleixner
2018-04-30  0:06       ` [MODERATED] " Jon Masters

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