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From: "Mylène Josserand" <mylene.josserand@bootlin.com>
To: linux@armlinux.org.uk, maxime.ripard@bootlin.com, wens@csie.org,
	marc.zyngier@arm.com, mark.rutland@arm.com, robh+dt@kernel.org,
	horms@verge.net.au, geert@linux-m68k.org, magnus.damm@gmail.com
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	clabbe.montjoie@gmail.com, quentin.schulz@bootlin.com,
	thomas.petazzoni@bootlin.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mylene.josserand@bootlin.com
Subject: [PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF
Date: Tue,  1 May 2018 14:31:25 +0200	[thread overview]
Message-ID: <20180501123131.7738-7-mylene.josserand@bootlin.com> (raw)
In-Reply-To: <20180501123131.7738-1-mylene.josserand@bootlin.com>

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/common/Makefile              |  1 +
 arch/arm/common/secure_cntvoff.S      | 31 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/secure_cntvoff.h |  8 ++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
 obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
+obj-$(CONFIG_SMP)		+= secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM)		+= mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
 CFLAGS_REMOVE_mcpm_entry.o	= -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index 000000000000..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(secure_cntvoff_init)
+	.arch	armv7-a
+	/*
+	 * CNTVOFF has to be initialized either from non-secure Hypervisor
+	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+	 * then it should be handled by the secure code
+	 */
+	cps	#MON_MODE
+	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
+	orr	r0, r1, #1
+	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
+	isb
+	mov	r0, #0
+	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
+	isb
+	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
+	isb
+	cps	#SVC_MODE
+	ret	lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index 000000000000..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

WARNING: multiple messages have this Message-ID
From: mylene.josserand@bootlin.com (Mylène Josserand)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF
Date: Tue,  1 May 2018 14:31:25 +0200	[thread overview]
Message-ID: <20180501123131.7738-7-mylene.josserand@bootlin.com> (raw)
In-Reply-To: <20180501123131.7738-1-mylene.josserand@bootlin.com>

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/common/Makefile              |  1 +
 arch/arm/common/secure_cntvoff.S      | 31 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/secure_cntvoff.h |  8 ++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
 obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
+obj-$(CONFIG_SMP)		+= secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM)		+= mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
 CFLAGS_REMOVE_mcpm_entry.o	= -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index 000000000000..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(secure_cntvoff_init)
+	.arch	armv7-a
+	/*
+	 * CNTVOFF has to be initialized either from non-secure Hypervisor
+	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+	 * then it should be handled by the secure code
+	 */
+	cps	#MON_MODE
+	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
+	orr	r0, r1, #1
+	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
+	isb
+	mov	r0, #0
+	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
+	isb
+	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
+	isb
+	cps	#SVC_MODE
+	ret	lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index 000000000000..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

  parent reply	other threads:[~2018-05-01 12:34 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-01 12:31 [PATCH v8 00/12] Sunxi: Add SMP support on A83T Mylène Josserand
2018-05-01 12:31 ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 01/12] ARM: Allow this header to be included by assembly files Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02 13:18   ` Maxime Ripard
2018-05-02 13:18     ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` Mylène Josserand [this message]
2018-05-01 12:31   ` [PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 07/12] ARM: sunxi: " Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02 13:08   ` Maxime Ripard
2018-05-02 13:08     ` Maxime Ripard
2018-05-02 13:28     ` Mylène Josserand
2018-05-02 13:28       ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02 13:09   ` Maxime Ripard
2018-05-02 13:09     ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02 13:14   ` Maxime Ripard
2018-05-02 13:14     ` Maxime Ripard
2018-05-01 12:31 ` [PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-01 12:31 ` [PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff Mylène Josserand
2018-05-01 12:31   ` Mylène Josserand
2018-05-02  6:36   ` Simon Horman
2018-05-02  6:36     ` Simon Horman
2018-05-02 13:18     ` Maxime Ripard
2018-05-02 13:18       ` Maxime Ripard

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