[PATCH] drm/i915/psr: vbt change for psr

[PATCH] drm/i915/psr: vbt change for psr

[vathsala nagaraju]

From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to kbl and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
    Handle option 2 in default condition.
    Print oustide range value.
    For negetive values default to 2500us

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
 drivers/gpu/drm/i915/intel_bios.c | 46 +++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
 4 files changed, 70 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6268a51..a189382 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1077,8 +1077,8 @@ struct intel_vbt_data {
 		bool require_aux_wakeup;
 		int idle_frames;
 		enum psr_lines_to_wait lines_to_wait;
-		int tp1_wakeup_time;
-		int tp2_tp3_wakeup_time;
+		int tp1_wakeup_time_us;
+		int tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 197c966..6bbd0b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4084,10 +4084,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500		(0<<8)
-#define   EDP_PSR2_TP2_TIME_100		(1<<8)
-#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
-#define   EDP_PSR2_TP2_TIME_50		(3<<8)
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 702d3fa..bb61ad8 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -687,8 +687,50 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+	/*
+	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+	 * Old decimal value is wake up time in multiples of 100 us.
+	 */
+	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
+		switch (psr_table->tp1_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			if (psr_table->tp1_wakeup_time != 2)
+				DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+						psr_table->tp1_wakeup_time);
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+			break;
+		}
+
+		switch (psr_table->tp2_tp3_wakeup_time) {
+		case 0:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+			break;
+		case 1:
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+			break;
+		case 3:
+			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+			break;
+		default:
+			if (psr_table->tp2_tp3_wakeup_time != 2)
+				DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \
+						defaulting to max value 2500us\n", psr_table->tp2_tp3_wakeup_time);
+			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+		break;
+		}
+	} else {
+		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6233a32..f03dfba 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
 
-	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-		val |= EDP_PSR_TP1_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-		val |= EDP_PSR_TP1_TIME_500us;
-	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP1_TIME_0us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
+	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP1_TIME_500us;
 	else
-		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR_TP2_TP3_TIME_2500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-		val |= EDP_PSR2_TP2_TIME_2500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-		val |= EDP_PSR2_TP2_TIME_500;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-		val |= EDP_PSR2_TP2_TIME_100;
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+		val |= EDP_PSR2_TP2_TIME_50us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		val |= EDP_PSR2_TP2_TIME_100us;
+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		val |= EDP_PSR2_TP2_TIME_500us;
 	else
-		val |= EDP_PSR2_TP2_TIME_50;
+		val |= EDP_PSR2_TP2_TIME_2500us;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
-- 
1.9.1

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✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: vbt change for psr (rev5)
URL   : https://patchwork.freedesktop.org/series/41289/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d6164e2f12bf drm/i915/psr: vbt change for psr
-:67: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:4087:
+#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
                                  	  ^

-:68: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#68: FILE: drivers/gpu/drm/i915/i915_reg.h:4088:
+#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
                                  	  ^

-:69: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#69: FILE: drivers/gpu/drm/i915/i915_reg.h:4089:
+#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
                                   	  ^

-:70: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#70: FILE: drivers/gpu/drm/i915/i915_reg.h:4090:
+#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
                                 	  ^

-:102: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#102: FILE: drivers/gpu/drm/i915/intel_bios.c:708:
+				DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+						psr_table->tp1_wakeup_time);

-:119: WARNING:LONG_LINE: line over 100 characters
#119: FILE: drivers/gpu/drm/i915/intel_bios.c:725:
+				DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \

-:119: WARNING:LINE_CONTINUATIONS: Avoid line continuations in quoted strings
#119: FILE: drivers/gpu/drm/i915/intel_bios.c:725:
+				DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \

-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/intel_bios.c:726:
+						defaulting to max value 2500us\n", psr_table->tp2_tp3_wakeup_time);

total: 0 errors, 3 warnings, 5 checks, 133 lines checked

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Re: [PATCH] drm/i915/psr: vbt change for psr

[Jani Nikula]

On Thu, 03 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not  mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to  provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to kbl and version 209+ to unblock google.
>
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
>     move the 165 version check to intel_bios.c
> v3: Jani
>     Move the abstraction to intel_bios.
> v4: Jani
>     Rename tp*_wakeup_time to have "us" suffix.
>     For values outside range[0-3],default to max 2500us.
>     Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
>     Handle option 2 in default condition.
>     Print oustide range value.
>     For negetive values default to 2500us
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
>
> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h   |  8 +++----
>  drivers/gpu/drm/i915/intel_bios.c | 46 +++++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_psr.c  | 39 +++++++++++++++++----------------
>  4 files changed, 70 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6268a51..a189382 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1077,8 +1077,8 @@ struct intel_vbt_data {
>  		bool require_aux_wakeup;
>  		int idle_frames;
>  		enum psr_lines_to_wait lines_to_wait;
> -		int tp1_wakeup_time;
> -		int tp2_tp3_wakeup_time;
> +		int tp1_wakeup_time_us;
> +		int tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 197c966..6bbd0b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4084,10 +4084,10 @@ enum {
>  #define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
> -#define   EDP_PSR2_TP2_TIME_500		(0<<8)
> -#define   EDP_PSR2_TP2_TIME_100		(1<<8)
> -#define   EDP_PSR2_TP2_TIME_2500	(2<<8)
> -#define   EDP_PSR2_TP2_TIME_50		(3<<8)
> +#define   EDP_PSR2_TP2_TIME_500us	(0<<8)
> +#define   EDP_PSR2_TP2_TIME_100us	(1<<8)
> +#define   EDP_PSR2_TP2_TIME_2500us	(2<<8)
> +#define   EDP_PSR2_TP2_TIME_50us	(3<<8)
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 702d3fa..bb61ad8 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -687,8 +687,50 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> +	/*
> +	 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
> +	 * Old decimal value is wake up time in multiples of 100 us.
> +	 */
> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) {
> +		switch (psr_table->tp1_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			if (psr_table->tp1_wakeup_time != 2)
> +				DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
> +						psr_table->tp1_wakeup_time);
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
> +			break;
> +		}

		default:
			DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", psr_table->tp1_wakeup_time);
                        /* fallthrough */
		case 2:
			dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
			break;

> +
> +		switch (psr_table->tp2_tp3_wakeup_time) {
> +		case 0:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
> +			break;
> +		case 1:
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
> +			break;
> +		case 3:
> +			dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
> +			break;
> +		default:
> +			if (psr_table->tp2_tp3_wakeup_time != 2)
> +				DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], \
> +						defaulting to max value 2500us\n", psr_table->tp2_tp3_wakeup_time);
> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
> +		break;
> +		}
> +	} else {
> +		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6233a32..f03dfba 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	if (dev_priv->psr.link_standby)
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> -		val |= EDP_PSR_TP1_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> -		val |= EDP_PSR_TP1_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP1_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP1_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_2500us;
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> +		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR_TP2_TP3_TIME_500us;
>  	else
> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
> @@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> -		val |= EDP_PSR2_TP2_TIME_2500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> -		val |= EDP_PSR2_TP2_TIME_500;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
> -		val |= EDP_PSR2_TP2_TIME_100;
> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> +	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +		val |= EDP_PSR2_TP2_TIME_50us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +		val |= EDP_PSR2_TP2_TIME_100us;
> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
> -		val |= EDP_PSR2_TP2_TIME_50;
> +		val |= EDP_PSR2_TP2_TIME_2500us;
>  
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }

-- 
Jani Nikula, Intel Open Source Technology Center
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✗ Fi.CI.BAT: failure for drm/i915/psr: vbt change for psr (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: vbt change for psr (rev5)
URL   : https://patchwork.freedesktop.org/series/41289/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4128 -> Patchwork_8892 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8892 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8892, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8892:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_module_reload@basic-reload:
      fi-bsw-n3050:       PASS -> DMESG-FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_8892 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-skl-guc:         PASS -> FAIL (fdo#104699) +1

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    igt@gem_wait@basic-wait-all:
      fi-bxt-dsi:         PASS -> FAIL (fdo#106125)

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-4200u:       PASS -> DMESG-FAIL (fdo#102614)

    
    ==== Possible fixes ====

    igt@kms_chamelium@dp-crc-fast:
      fi-kbl-7500u:       DMESG-FAIL (fdo#103841) -> PASS

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-cnl-psr:         FAIL (fdo#100368) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-cnl-y3:          DMESG-WARN (fdo#104951) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#104699 https://bugs.freedesktop.org/show_bug.cgi?id=104699
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#106125 https://bugs.freedesktop.org/show_bug.cgi?id=106125


== Participating hosts (38 -> 36) ==

  Additional (1): fi-glk-j4005 
  Missing    (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4128 -> Patchwork_8892

  CI_DRM_4128: 942a7c23ce721bb617fc8d0757fc89a6c3972fe0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4458: 43761534c6482dc67b9c3d8eeecd425ef40b3c4c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8892: d6164e2f12bf129053bd3e39b916e488ef400034 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4458: f74d92e704849610364b4474a2c67ea2008c14e0 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

d6164e2f12bf drm/i915/psr: vbt change for psr

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8892/issues.html
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