From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PATCH 08/13] target/openrisc: Convert dec_logic
Date: Thu, 3 May 2018 22:40:25 -0700 [thread overview]
Message-ID: <20180504054030.24527-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180504054030.24527-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/translate.c | 62 +++++++++++++++++++-------------------------
target/openrisc/insns.decode | 6 +++++
2 files changed, 32 insertions(+), 36 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 8ca01e1a33..f2f9a0c0d2 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -999,42 +999,36 @@ static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn)
return true;
}
-static void dec_logic(DisasContext *dc, uint32_t insn)
+static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn)
{
- uint32_t op0;
- uint32_t rd, ra, L6, S6;
- op0 = extract32(insn, 6, 2);
- rd = extract32(insn, 21, 5);
- ra = extract32(insn, 16, 5);
- L6 = extract32(insn, 0, 6);
- S6 = L6 & (TARGET_LONG_BITS - 1);
+ LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l);
+ check_r0_write(a->d);
+ tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
+ return true;
+}
- check_r0_write(rd);
- switch (op0) {
- case 0x00: /* l.slli */
- LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6);
- tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6);
- break;
+static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn)
+{
+ LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l);
+ check_r0_write(a->d);
+ tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
+ return true;
+}
- case 0x01: /* l.srli */
- LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6);
- tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6);
- break;
+static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn)
+{
+ LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l);
+ check_r0_write(a->d);
+ tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
+ return true;
+}
- case 0x02: /* l.srai */
- LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6);
- tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6);
- break;
-
- case 0x03: /* l.rori */
- LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6);
- tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6);
- break;
-
- default:
- gen_illegal_exception(dc);
- break;
- }
+static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
+{
+ LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l);
+ check_r0_write(a->d);
+ tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
+ return true;
}
static void dec_M(DisasContext *dc, uint32_t insn)
@@ -1491,10 +1485,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
dec_M(dc, insn);
break;
- case 0x2e:
- dec_logic(dc, insn);
- break;
-
case 0x2f:
dec_compi(dc, insn);
break;
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode
index 7240c6fb77..fb8ba5812a 100644
--- a/target/openrisc/insns.decode
+++ b/target/openrisc/insns.decode
@@ -20,6 +20,7 @@
&dab d a b
&da d a
&ab a b
+&dal d a l
####
# System Instructions
@@ -130,3 +131,8 @@ l_mac 110001 ----- a:5 b:5 ------- 0001
l_macu 110001 ----- a:5 b:5 ------- 0011
l_msb 110001 ----- a:5 b:5 ------- 0010
l_msbu 110001 ----- a:5 b:5 ------- 0100
+
+l_slli 101110 d:5 a:5 -------- 00 l:6
+l_srli 101110 d:5 a:5 -------- 01 l:6
+l_srai 101110 d:5 a:5 -------- 10 l:6
+l_rori 101110 d:5 a:5 -------- 11 l:6
--
2.14.3
next prev parent reply other threads:[~2018-05-04 5:40 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-04 5:40 [Qemu-devel] [PATCH 00/13] target/openrisc: Convert to decodetree.py Richard Henderson
2018-05-04 5:40 ` [Qemu-devel] [PATCH 01/13] target-openrisc: Write back result before FPE exception Richard Henderson
2018-05-05 5:19 ` Stafford Horne
2018-05-05 11:08 ` BAndViG
2018-05-04 5:40 ` [Qemu-devel] [PATCH 02/13] target/openrisc: Start conversion to decodetree.py Richard Henderson
2018-05-05 5:22 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 03/13] target/openrisc: Convert branch insns Richard Henderson
2018-05-05 5:25 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 04/13] target/openrisc: Convert memory insns Richard Henderson
2018-05-05 5:27 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 05/13] target/openrisc: Convert remainder of dec_misc insns Richard Henderson
2018-05-05 5:32 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 06/13] target/openrisc: Convert dec_calc Richard Henderson
2018-05-05 5:34 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 07/13] target/openrisc: Convert dec_mac Richard Henderson
2018-05-05 5:35 ` Stafford Horne
2018-05-04 5:40 ` Richard Henderson [this message]
2018-05-05 5:37 ` [Qemu-devel] [PATCH 08/13] target/openrisc: Convert dec_logic Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 09/13] target/openrisc: Convert dec_M Richard Henderson
2018-05-05 5:39 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 10/13] target/openrisc: Convert dec_comp Richard Henderson
2018-05-05 5:39 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 11/13] target/openrisc: Convert dec_compi Richard Henderson
2018-05-05 5:41 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 12/13] target/openrisc: Convert dec_float Richard Henderson
2018-05-05 5:45 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 13/13] target/openrisc: Merge disas_openrisc_insn Richard Henderson
2018-05-05 5:46 ` Stafford Horne
2018-05-05 5:49 ` [Qemu-devel] [PATCH 00/13] target/openrisc: Convert to decodetree.py Stafford Horne
2018-05-05 15:15 ` Richard Henderson
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