From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751394AbeEDLQD (ORCPT ); Fri, 4 May 2018 07:16:03 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:39325 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751106AbeEDLQC (ORCPT ); Fri, 4 May 2018 07:16:02 -0400 From: Sebastian Andrzej Siewior To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, Tony Luck , Borislav Petkov , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-edac@vger.kernel.org, Sebastian Andrzej Siewior Subject: [PATCH] x86: Convert mce timer to hrtimer Date: Fri, 4 May 2018 13:14:58 +0200 Message-Id: <20180504111459.24825-1-bigeasy@linutronix.de> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thomas Gleixner mce_timer is started in atomic contexts of cpu bringup. This results in might_sleep() warnings on RT. Convert mce_timer to a hrtimer to avoid this. Cc: Tony Luck Cc: Borislav Petkov Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: linux-edac@vger.kernel.org (open list:X86 MCE INFRASTRUCTURE) Signed-off-by: Thomas Gleixner fold in: |From: Mike Galbraith |Date: Wed, 29 May 2013 13:52:13 +0200 |Subject: [PATCH] x86/mce: fix mce timer interval | |Seems mce timer fire at the wrong frequency in -rt kernels since roughly |forever due to 32 bit overflow. 3.8-rt is also missing a multiplier. | |Add missing us -> ns conversion and 32 bit overflow prevention. | |Signed-off-by: Mike Galbraith |[bigeasy: use ULL instead of u64 cast] Signed-off-by: Sebastian Andrzej Siewior --- arch/x86/kernel/cpu/mcheck/mce.c | 52 +++++++++++++++++++---------------= ----- 1 file changed, 26 insertions(+), 26 deletions(-) --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -41,6 +41,7 @@ #include #include #include +#include #include =20 #include @@ -1358,7 +1359,7 @@ int memory_failure(unsigned long pfn, in static unsigned long check_interval =3D INITIAL_CHECK_INTERVAL; =20 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ -static DEFINE_PER_CPU(struct timer_list, mce_timer); +static DEFINE_PER_CPU(struct hrtimer, mce_timer); =20 static unsigned long mce_adjust_timer_default(unsigned long interval) { @@ -1367,26 +1368,18 @@ static unsigned long mce_adjust_timer_de =20 static unsigned long (*mce_adjust_timer)(unsigned long interval) =3D mce_a= djust_timer_default; =20 -static void __start_timer(struct timer_list *t, unsigned long interval) +static void __start_timer(struct hrtimer *t, unsigned long iv) { - unsigned long when =3D jiffies + interval; - unsigned long flags; - - local_irq_save(flags); - - if (!timer_pending(t) || time_before(when, t->expires)) - mod_timer(t, round_jiffies(when)); - - local_irq_restore(flags); + if (!iv) + return; + hrtimer_start_range_ns(t, ns_to_ktime(jiffies_to_usecs(iv) * 1000ULL), + 0, HRTIMER_MODE_REL_PINNED); } =20 -static void mce_timer_fn(struct timer_list *t) +static enum hrtimer_restart mce_timer_fn(struct hrtimer *timer) { - struct timer_list *cpu_t =3D this_cpu_ptr(&mce_timer); unsigned long iv; =20 - WARN_ON(cpu_t !=3D t); - iv =3D __this_cpu_read(mce_next_interval); =20 if (mce_available(this_cpu_ptr(&cpu_info))) { @@ -1409,7 +1402,11 @@ static void mce_timer_fn(struct timer_li =20 done: __this_cpu_write(mce_next_interval, iv); - __start_timer(t, iv); + if (!iv) + return HRTIMER_NORESTART; + + hrtimer_forward_now(timer, ns_to_ktime(jiffies_to_nsecs(iv))); + return HRTIMER_RESTART; } =20 /* @@ -1417,7 +1414,7 @@ static void mce_timer_fn(struct timer_li */ void mce_timer_kick(unsigned long interval) { - struct timer_list *t =3D this_cpu_ptr(&mce_timer); + struct hrtimer *t =3D this_cpu_ptr(&mce_timer); unsigned long iv =3D __this_cpu_read(mce_next_interval); =20 __start_timer(t, interval); @@ -1432,7 +1429,7 @@ static void mce_timer_delete_all(void) int cpu; =20 for_each_online_cpu(cpu) - del_timer_sync(&per_cpu(mce_timer, cpu)); + hrtimer_cancel(&per_cpu(mce_timer, cpu)); } =20 /* @@ -1761,7 +1758,7 @@ static void __mcheck_cpu_clear_vendor(st } } =20 -static void mce_start_timer(struct timer_list *t) +static void mce_start_timer(struct hrtimer *t) { unsigned long iv =3D check_interval * HZ; =20 @@ -1774,16 +1771,19 @@ static void mce_start_timer(struct timer =20 static void __mcheck_cpu_setup_timer(void) { - struct timer_list *t =3D this_cpu_ptr(&mce_timer); + struct hrtimer *t =3D this_cpu_ptr(&mce_timer); =20 - timer_setup(t, mce_timer_fn, TIMER_PINNED); + hrtimer_init(t, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + t->function =3D mce_timer_fn; } =20 static void __mcheck_cpu_init_timer(void) { - struct timer_list *t =3D this_cpu_ptr(&mce_timer); + struct hrtimer *t =3D this_cpu_ptr(&mce_timer); + + hrtimer_init(t, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + t->function =3D mce_timer_fn; =20 - timer_setup(t, mce_timer_fn, TIMER_PINNED); mce_start_timer(t); } =20 @@ -2285,7 +2285,7 @@ static int mce_cpu_dead(unsigned int cpu =20 static int mce_cpu_online(unsigned int cpu) { - struct timer_list *t =3D this_cpu_ptr(&mce_timer); + struct hrtimer *t =3D this_cpu_ptr(&mce_timer); int ret; =20 mce_device_create(cpu); @@ -2302,10 +2302,10 @@ static int mce_cpu_online(unsigned int c =20 static int mce_cpu_pre_down(unsigned int cpu) { - struct timer_list *t =3D this_cpu_ptr(&mce_timer); + struct hrtimer *t =3D this_cpu_ptr(&mce_timer); =20 mce_disable_cpu(); - del_timer_sync(t); + hrtimer_cancel(t); mce_threshold_remove_device(cpu); mce_device_remove(cpu); return 0; From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: x86: Convert mce timer to hrtimer From: Sebastian Andrzej Siewior Message-Id: <20180504111459.24825-1-bigeasy@linutronix.de> Date: Fri, 4 May 2018 13:14:58 +0200 To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, Tony Luck , Borislav Petkov , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-edac@vger.kernel.org, Sebastian Andrzej Siewior List-ID: RnJvbTogVGhvbWFzIEdsZWl4bmVyIDx0Z2x4QGxpbnV0cm9uaXguZGU+CgptY2VfdGltZXIgaXMg c3RhcnRlZCBpbiBhdG9taWMgY29udGV4dHMgb2YgY3B1IGJyaW5ndXAuIFRoaXMgcmVzdWx0cwpp biBtaWdodF9zbGVlcCgpIHdhcm5pbmdzIG9uIFJULiBDb252ZXJ0IG1jZV90aW1lciB0byBhIGhy dGltZXIgdG8KYXZvaWQgdGhpcy4KCkNjOiBUb255IEx1Y2sgPHRvbnkubHVja0BpbnRlbC5jb20+ CkNjOiBCb3Jpc2xhdiBQZXRrb3YgPGJwQGFsaWVuOC5kZT4KQ2M6IEluZ28gTW9sbmFyIDxtaW5n b0ByZWRoYXQuY29tPgpDYzogIkguIFBldGVyIEFudmluIiA8aHBhQHp5dG9yLmNvbT4KQ2M6IHg4 NkBrZXJuZWwub3JnCkNjOiBsaW51eC1lZGFjQHZnZXIua2VybmVsLm9yZyAob3BlbiBsaXN0Olg4 NiBNQ0UgSU5GUkFTVFJVQ1RVUkUpClNpZ25lZC1vZmYtYnk6IFRob21hcyBHbGVpeG5lciA8dGds eEBsaW51dHJvbml4LmRlPgpmb2xkIGluOgp8RnJvbTogTWlrZSBHYWxicmFpdGggPGJpdGJ1Y2tl dEBvbmxpbmUuZGU+CnxEYXRlOiBXZWQsIDI5IE1heSAyMDEzIDEzOjUyOjEzICswMjAwCnxTdWJq ZWN0OiBbUEFUQ0hdIHg4Ni9tY2U6IGZpeCBtY2UgdGltZXIgaW50ZXJ2YWwKfAp8U2VlbXMgbWNl IHRpbWVyIGZpcmUgYXQgdGhlIHdyb25nIGZyZXF1ZW5jeSBpbiAtcnQga2VybmVscyBzaW5jZSBy b3VnaGx5Cnxmb3JldmVyIGR1ZSB0byAzMiBiaXQgb3ZlcmZsb3cuICAzLjgtcnQgaXMgYWxzbyBt aXNzaW5nIGEgbXVsdGlwbGllci4KfAp8QWRkIG1pc3NpbmcgdXMgLT4gbnMgY29udmVyc2lvbiBh bmQgMzIgYml0IG92ZXJmbG93IHByZXZlbnRpb24uCnwKfFNpZ25lZC1vZmYtYnk6IE1pa2UgR2Fs YnJhaXRoIDxiaXRidWNrZXRAb25saW5lLmRlPgp8W2JpZ2Vhc3k6IHVzZSBVTEwgaW5zdGVhZCBv ZiB1NjQgY2FzdF0KU2lnbmVkLW9mZi1ieTogU2ViYXN0aWFuIEFuZHJ6ZWogU2lld2lvciA8Ymln ZWFzeUBsaW51dHJvbml4LmRlPgotLS0KIGFyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZS5j IHwgICA1MiArKysrKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0tLS0tLS0tLS0KIDEgZmlsZSBj aGFuZ2VkLCAyNiBpbnNlcnRpb25zKCspLCAyNiBkZWxldGlvbnMoLSkKCi0tClRvIHVuc3Vic2Ny aWJlIGZyb20gdGhpcyBsaXN0OiBzZW5kIHRoZSBsaW5lICJ1bnN1YnNjcmliZSBsaW51eC1lZGFj IiBpbgp0aGUgYm9keSBvZiBhIG1lc3NhZ2UgdG8gbWFqb3Jkb21vQHZnZXIua2VybmVsLm9yZwpN b3JlIG1ham9yZG9tbyBpbmZvIGF0ICBodHRwOi8vdmdlci5rZXJuZWwub3JnL21ham9yZG9tby1p bmZvLmh0bWwKCi0tLSBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZS5jCisrKyBiL2Fy Y2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZS5jCkBAIC00MSw2ICs0MSw3IEBACiAjaW5jbHVk ZSA8bGludXgvZGVidWdmcy5oPgogI2luY2x1ZGUgPGxpbnV4L2lycV93b3JrLmg+CiAjaW5jbHVk ZSA8bGludXgvZXhwb3J0Lmg+CisjaW5jbHVkZSA8bGludXgvamlmZmllcy5oPgogI2luY2x1ZGUg PGxpbnV4L2p1bXBfbGFiZWwuaD4KIAogI2luY2x1ZGUgPGFzbS9pbnRlbC1mYW1pbHkuaD4KQEAg LTEzNTgsNyArMTM1OSw3IEBAIGludCBtZW1vcnlfZmFpbHVyZSh1bnNpZ25lZCBsb25nIHBmbiwg aW4KIHN0YXRpYyB1bnNpZ25lZCBsb25nIGNoZWNrX2ludGVydmFsID0gSU5JVElBTF9DSEVDS19J TlRFUlZBTDsKIAogc3RhdGljIERFRklORV9QRVJfQ1BVKHVuc2lnbmVkIGxvbmcsIG1jZV9uZXh0 X2ludGVydmFsKTsgLyogaW4gamlmZmllcyAqLwotc3RhdGljIERFRklORV9QRVJfQ1BVKHN0cnVj dCB0aW1lcl9saXN0LCBtY2VfdGltZXIpOworc3RhdGljIERFRklORV9QRVJfQ1BVKHN0cnVjdCBo cnRpbWVyLCBtY2VfdGltZXIpOwogCiBzdGF0aWMgdW5zaWduZWQgbG9uZyBtY2VfYWRqdXN0X3Rp bWVyX2RlZmF1bHQodW5zaWduZWQgbG9uZyBpbnRlcnZhbCkKIHsKQEAgLTEzNjcsMjYgKzEzNjgs MTggQEAgc3RhdGljIHVuc2lnbmVkIGxvbmcgbWNlX2FkanVzdF90aW1lcl9kZQogCiBzdGF0aWMg dW5zaWduZWQgbG9uZyAoKm1jZV9hZGp1c3RfdGltZXIpKHVuc2lnbmVkIGxvbmcgaW50ZXJ2YWwp ID0gbWNlX2FkanVzdF90aW1lcl9kZWZhdWx0OwogCi1zdGF0aWMgdm9pZCBfX3N0YXJ0X3RpbWVy KHN0cnVjdCB0aW1lcl9saXN0ICp0LCB1bnNpZ25lZCBsb25nIGludGVydmFsKQorc3RhdGljIHZv aWQgX19zdGFydF90aW1lcihzdHJ1Y3QgaHJ0aW1lciAqdCwgdW5zaWduZWQgbG9uZyBpdikKIHsK LQl1bnNpZ25lZCBsb25nIHdoZW4gPSBqaWZmaWVzICsgaW50ZXJ2YWw7Ci0JdW5zaWduZWQgbG9u ZyBmbGFnczsKLQotCWxvY2FsX2lycV9zYXZlKGZsYWdzKTsKLQotCWlmICghdGltZXJfcGVuZGlu Zyh0KSB8fCB0aW1lX2JlZm9yZSh3aGVuLCB0LT5leHBpcmVzKSkKLQkJbW9kX3RpbWVyKHQsIHJv dW5kX2ppZmZpZXMod2hlbikpOwotCi0JbG9jYWxfaXJxX3Jlc3RvcmUoZmxhZ3MpOworCWlmICgh aXYpCisJCXJldHVybjsKKwlocnRpbWVyX3N0YXJ0X3JhbmdlX25zKHQsIG5zX3RvX2t0aW1lKGpp ZmZpZXNfdG9fdXNlY3MoaXYpICogMTAwMFVMTCksCisJCQkgICAgICAgMCwgSFJUSU1FUl9NT0RF X1JFTF9QSU5ORUQpOwogfQogCi1zdGF0aWMgdm9pZCBtY2VfdGltZXJfZm4oc3RydWN0IHRpbWVy X2xpc3QgKnQpCitzdGF0aWMgZW51bSBocnRpbWVyX3Jlc3RhcnQgbWNlX3RpbWVyX2ZuKHN0cnVj dCBocnRpbWVyICp0aW1lcikKIHsKLQlzdHJ1Y3QgdGltZXJfbGlzdCAqY3B1X3QgPSB0aGlzX2Nw dV9wdHIoJm1jZV90aW1lcik7CiAJdW5zaWduZWQgbG9uZyBpdjsKIAotCVdBUk5fT04oY3B1X3Qg IT0gdCk7Ci0KIAlpdiA9IF9fdGhpc19jcHVfcmVhZChtY2VfbmV4dF9pbnRlcnZhbCk7CiAKIAlp ZiAobWNlX2F2YWlsYWJsZSh0aGlzX2NwdV9wdHIoJmNwdV9pbmZvKSkpIHsKQEAgLTE0MDksNyAr MTQwMiwxMSBAQCBzdGF0aWMgdm9pZCBtY2VfdGltZXJfZm4oc3RydWN0IHRpbWVyX2xpCiAKIGRv bmU6CiAJX190aGlzX2NwdV93cml0ZShtY2VfbmV4dF9pbnRlcnZhbCwgaXYpOwotCV9fc3RhcnRf dGltZXIodCwgaXYpOworCWlmICghaXYpCisJCXJldHVybiBIUlRJTUVSX05PUkVTVEFSVDsKKwor CWhydGltZXJfZm9yd2FyZF9ub3codGltZXIsIG5zX3RvX2t0aW1lKGppZmZpZXNfdG9fbnNlY3Mo aXYpKSk7CisJcmV0dXJuIEhSVElNRVJfUkVTVEFSVDsKIH0KIAogLyoKQEAgLTE0MTcsNyArMTQx NCw3IEBAIHN0YXRpYyB2b2lkIG1jZV90aW1lcl9mbihzdHJ1Y3QgdGltZXJfbGkKICAqLwogdm9p ZCBtY2VfdGltZXJfa2ljayh1bnNpZ25lZCBsb25nIGludGVydmFsKQogewotCXN0cnVjdCB0aW1l cl9saXN0ICp0ID0gdGhpc19jcHVfcHRyKCZtY2VfdGltZXIpOworCXN0cnVjdCBocnRpbWVyICp0 ID0gdGhpc19jcHVfcHRyKCZtY2VfdGltZXIpOwogCXVuc2lnbmVkIGxvbmcgaXYgPSBfX3RoaXNf Y3B1X3JlYWQobWNlX25leHRfaW50ZXJ2YWwpOwogCiAJX19zdGFydF90aW1lcih0LCBpbnRlcnZh bCk7CkBAIC0xNDMyLDcgKzE0MjksNyBAQCBzdGF0aWMgdm9pZCBtY2VfdGltZXJfZGVsZXRlX2Fs bCh2b2lkKQogCWludCBjcHU7CiAKIAlmb3JfZWFjaF9vbmxpbmVfY3B1KGNwdSkKLQkJZGVsX3Rp bWVyX3N5bmMoJnBlcl9jcHUobWNlX3RpbWVyLCBjcHUpKTsKKwkJaHJ0aW1lcl9jYW5jZWwoJnBl cl9jcHUobWNlX3RpbWVyLCBjcHUpKTsKIH0KIAogLyoKQEAgLTE3NjEsNyArMTc1OCw3IEBAIHN0 YXRpYyB2b2lkIF9fbWNoZWNrX2NwdV9jbGVhcl92ZW5kb3Ioc3QKIAl9CiB9CiAKLXN0YXRpYyB2 b2lkIG1jZV9zdGFydF90aW1lcihzdHJ1Y3QgdGltZXJfbGlzdCAqdCkKK3N0YXRpYyB2b2lkIG1j ZV9zdGFydF90aW1lcihzdHJ1Y3QgaHJ0aW1lciAqdCkKIHsKIAl1bnNpZ25lZCBsb25nIGl2ID0g Y2hlY2tfaW50ZXJ2YWwgKiBIWjsKIApAQCAtMTc3NCwxNiArMTc3MSwxOSBAQCBzdGF0aWMgdm9p ZCBtY2Vfc3RhcnRfdGltZXIoc3RydWN0IHRpbWVyCiAKIHN0YXRpYyB2b2lkIF9fbWNoZWNrX2Nw dV9zZXR1cF90aW1lcih2b2lkKQogewotCXN0cnVjdCB0aW1lcl9saXN0ICp0ID0gdGhpc19jcHVf cHRyKCZtY2VfdGltZXIpOworCXN0cnVjdCBocnRpbWVyICp0ID0gdGhpc19jcHVfcHRyKCZtY2Vf dGltZXIpOwogCi0JdGltZXJfc2V0dXAodCwgbWNlX3RpbWVyX2ZuLCBUSU1FUl9QSU5ORUQpOwor CWhydGltZXJfaW5pdCh0LCBDTE9DS19NT05PVE9OSUMsIEhSVElNRVJfTU9ERV9SRUwpOworCXQt PmZ1bmN0aW9uID0gbWNlX3RpbWVyX2ZuOwogfQogCiBzdGF0aWMgdm9pZCBfX21jaGVja19jcHVf aW5pdF90aW1lcih2b2lkKQogewotCXN0cnVjdCB0aW1lcl9saXN0ICp0ID0gdGhpc19jcHVfcHRy KCZtY2VfdGltZXIpOworCXN0cnVjdCBocnRpbWVyICp0ID0gdGhpc19jcHVfcHRyKCZtY2VfdGlt ZXIpOworCisJaHJ0aW1lcl9pbml0KHQsIENMT0NLX01PTk9UT05JQywgSFJUSU1FUl9NT0RFX1JF TCk7CisJdC0+ZnVuY3Rpb24gPSBtY2VfdGltZXJfZm47CiAKLQl0aW1lcl9zZXR1cCh0LCBtY2Vf dGltZXJfZm4sIFRJTUVSX1BJTk5FRCk7CiAJbWNlX3N0YXJ0X3RpbWVyKHQpOwogfQogCkBAIC0y Mjg1LDcgKzIyODUsNyBAQCBzdGF0aWMgaW50IG1jZV9jcHVfZGVhZCh1bnNpZ25lZCBpbnQgY3B1 CiAKIHN0YXRpYyBpbnQgbWNlX2NwdV9vbmxpbmUodW5zaWduZWQgaW50IGNwdSkKIHsKLQlzdHJ1 Y3QgdGltZXJfbGlzdCAqdCA9IHRoaXNfY3B1X3B0cigmbWNlX3RpbWVyKTsKKwlzdHJ1Y3QgaHJ0 aW1lciAqdCA9IHRoaXNfY3B1X3B0cigmbWNlX3RpbWVyKTsKIAlpbnQgcmV0OwogCiAJbWNlX2Rl dmljZV9jcmVhdGUoY3B1KTsKQEAgLTIzMDIsMTAgKzIzMDIsMTAgQEAgc3RhdGljIGludCBtY2Vf Y3B1X29ubGluZSh1bnNpZ25lZCBpbnQgYwogCiBzdGF0aWMgaW50IG1jZV9jcHVfcHJlX2Rvd24o dW5zaWduZWQgaW50IGNwdSkKIHsKLQlzdHJ1Y3QgdGltZXJfbGlzdCAqdCA9IHRoaXNfY3B1X3B0 cigmbWNlX3RpbWVyKTsKKwlzdHJ1Y3QgaHJ0aW1lciAqdCA9IHRoaXNfY3B1X3B0cigmbWNlX3Rp bWVyKTsKIAogCW1jZV9kaXNhYmxlX2NwdSgpOwotCWRlbF90aW1lcl9zeW5jKHQpOworCWhydGlt ZXJfY2FuY2VsKHQpOwogCW1jZV90aHJlc2hvbGRfcmVtb3ZlX2RldmljZShjcHUpOwogCW1jZV9k ZXZpY2VfcmVtb3ZlKGNwdSk7CiAJcmV0dXJuIDA7Cg==