[PATCH/RFT 0/3] mmc: renesas_sdhi: add support for r8a77965

[PATCH/RFT 0/3] mmc: renesas_sdhi: add support for r8a77965

[Yoshihiro Kaneko]

This series adds SDHI device support for r8a77965.

This series is based on the next branch of Ulf Hansson's mmc tree.

Masaharu Hayakawa (1):
  mmc: renesas_sdhi: Add r8a77965 support

Takeshi Kihara (2):
  pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions
  arm64: dts: r8a77965: Add SDHI device nodes

 Documentation/devicetree/bindings/mmc/tmio_mmc.txt |   1 +
 arch/arm64/boot/dts/renesas/r8a77965.dtsi          |  68 +++--
 drivers/mmc/host/renesas_sdhi_internal_dmac.c      |   2 +
 drivers/pinctrl/sh-pfc/pfc-r8a77965.c              | 326 +++++++++++++++++++++
 4 files changed, 377 insertions(+), 20 deletions(-)

-- 
1.9.1

[PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 326 ++++++++++++++++++++++++++++++++++
 1 file changed, 326 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index cea9d05..0350197 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1923,6 +1923,264 @@ enum {
 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
 };
 
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int sdhi0_data1_mux[] = {
+	SD0_DAT0_MARK,
+};
+
+static const unsigned int sdhi0_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+
+static const unsigned int sdhi0_data4_mux[] = {
+	SD0_DAT0_MARK, SD0_DAT1_MARK,
+	SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+
+static const unsigned int sdhi0_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+
+static const unsigned int sdhi0_ctrl_mux[] = {
+	SD0_CLK_MARK, SD0_CMD_MARK,
+};
+
+static const unsigned int sdhi0_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(3, 12),
+};
+
+static const unsigned int sdhi0_cd_mux[] = {
+	SD0_CD_MARK,
+};
+
+static const unsigned int sdhi0_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int sdhi0_wp_mux[] = {
+	SD0_WP_MARK,
+};
+
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 8),
+};
+
+static const unsigned int sdhi1_data1_mux[] = {
+	SD1_DAT0_MARK,
+};
+
+static const unsigned int sdhi1_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi1_data4_mux[] = {
+	SD1_DAT0_MARK, SD1_DAT1_MARK,
+	SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+
+static const unsigned int sdhi1_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+
+static const unsigned int sdhi1_ctrl_mux[] = {
+	SD1_CLK_MARK, SD1_CMD_MARK,
+};
+
+static const unsigned int sdhi1_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(3, 14),
+};
+
+static const unsigned int sdhi1_cd_mux[] = {
+	SD1_CD_MARK,
+};
+
+static const unsigned int sdhi1_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int sdhi1_wp_mux[] = {
+	SD1_WP_MARK,
+};
+
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(4, 2),
+};
+
+static const unsigned int sdhi2_data1_mux[] = {
+	SD2_DAT0_MARK,
+};
+
+static const unsigned int sdhi2_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+
+static const unsigned int sdhi2_data4_mux[] = {
+	SD2_DAT0_MARK, SD2_DAT1_MARK,
+	SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+
+static const unsigned int sdhi2_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
+	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
+	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi2_data8_mux[] = {
+	SD2_DAT0_MARK, SD2_DAT1_MARK,
+	SD2_DAT2_MARK, SD2_DAT3_MARK,
+	SD2_DAT4_MARK, SD2_DAT5_MARK,
+	SD2_DAT6_MARK, SD2_DAT7_MARK,
+};
+
+static const unsigned int sdhi2_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+
+static const unsigned int sdhi2_ctrl_mux[] = {
+	SD2_CLK_MARK, SD2_CMD_MARK,
+};
+
+static const unsigned int sdhi2_cd_a_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(4, 13),
+};
+
+static const unsigned int sdhi2_cd_a_mux[] = {
+	SD2_CD_A_MARK,
+};
+
+static const unsigned int sdhi2_cd_b_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(5, 10),
+};
+
+static const unsigned int sdhi2_cd_b_mux[] = {
+	SD2_CD_B_MARK,
+};
+
+static const unsigned int sdhi2_wp_a_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(4, 14),
+};
+
+static const unsigned int sdhi2_wp_a_mux[] = {
+	SD2_WP_A_MARK,
+};
+
+static const unsigned int sdhi2_wp_b_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(5, 11),
+};
+
+static const unsigned int sdhi2_wp_b_mux[] = {
+	SD2_WP_B_MARK,
+};
+
+static const unsigned int sdhi2_ds_pins[] = {
+	/* DS */
+	RCAR_GP_PIN(4, 6),
+};
+
+static const unsigned int sdhi2_ds_mux[] = {
+	SD2_DS_MARK,
+};
+
+/* - SDHI3 ------------------------------------------------------------------ */
+static const unsigned int sdhi3_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(4, 9),
+};
+
+static const unsigned int sdhi3_data1_mux[] = {
+	SD3_DAT0_MARK,
+};
+
+static const unsigned int sdhi3_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
+	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+};
+
+static const unsigned int sdhi3_data4_mux[] = {
+	SD3_DAT0_MARK, SD3_DAT1_MARK,
+	SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+
+static const unsigned int sdhi3_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
+	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
+	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+
+static const unsigned int sdhi3_data8_mux[] = {
+	SD3_DAT0_MARK, SD3_DAT1_MARK,
+	SD3_DAT2_MARK, SD3_DAT3_MARK,
+	SD3_DAT4_MARK, SD3_DAT5_MARK,
+	SD3_DAT6_MARK, SD3_DAT7_MARK,
+};
+
+static const unsigned int sdhi3_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
+};
+
+static const unsigned int sdhi3_ctrl_mux[] = {
+	SD3_CLK_MARK, SD3_CMD_MARK,
+};
+
+static const unsigned int sdhi3_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(4, 15),
+};
+
+static const unsigned int sdhi3_cd_mux[] = {
+	SD3_CD_MARK,
+};
+
+static const unsigned int sdhi3_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(4, 16),
+};
+
+static const unsigned int sdhi3_wp_mux[] = {
+	SD3_WP_MARK,
+};
+
+static const unsigned int sdhi3_ds_pins[] = {
+	/* DS */
+	RCAR_GP_PIN(4, 17),
+};
+
+static const unsigned int sdhi3_ds_mux[] = {
+	SD3_DS_MARK,
+};
+
 static const unsigned int usb0_mux[] = {
 	USB0_PWEN_MARK, USB0_OVC_MARK,
 };
@@ -1997,6 +2255,32 @@ enum {
 	SH_PFC_PIN_GROUP(usb0),
 	SH_PFC_PIN_GROUP(usb1),
 	SH_PFC_PIN_GROUP(usb30),
+	SH_PFC_PIN_GROUP(sdhi0_data1),
+	SH_PFC_PIN_GROUP(sdhi0_data4),
+	SH_PFC_PIN_GROUP(sdhi0_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_cd),
+	SH_PFC_PIN_GROUP(sdhi0_wp),
+	SH_PFC_PIN_GROUP(sdhi1_data1),
+	SH_PFC_PIN_GROUP(sdhi1_data4),
+	SH_PFC_PIN_GROUP(sdhi1_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_cd),
+	SH_PFC_PIN_GROUP(sdhi1_wp),
+	SH_PFC_PIN_GROUP(sdhi2_data1),
+	SH_PFC_PIN_GROUP(sdhi2_data4),
+	SH_PFC_PIN_GROUP(sdhi2_data8),
+	SH_PFC_PIN_GROUP(sdhi2_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_cd_a),
+	SH_PFC_PIN_GROUP(sdhi2_wp_a),
+	SH_PFC_PIN_GROUP(sdhi2_cd_b),
+	SH_PFC_PIN_GROUP(sdhi2_wp_b),
+	SH_PFC_PIN_GROUP(sdhi2_ds),
+	SH_PFC_PIN_GROUP(sdhi3_data1),
+	SH_PFC_PIN_GROUP(sdhi3_data4),
+	SH_PFC_PIN_GROUP(sdhi3_data8),
+	SH_PFC_PIN_GROUP(sdhi3_ctrl),
+	SH_PFC_PIN_GROUP(sdhi3_cd),
+	SH_PFC_PIN_GROUP(sdhi3_wp),
+	SH_PFC_PIN_GROUP(sdhi3_ds),
 };
 
 static const char * const avb_groups[] = {
@@ -2083,6 +2367,44 @@ enum {
 	"usb30",
 };
 
+static const char * const sdhi0_groups[] = {
+	"sdhi0_data1",
+	"sdhi0_data4",
+	"sdhi0_ctrl",
+	"sdhi0_cd",
+	"sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+	"sdhi1_data1",
+	"sdhi1_data4",
+	"sdhi1_ctrl",
+	"sdhi1_cd",
+	"sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+	"sdhi2_data1",
+	"sdhi2_data4",
+	"sdhi2_data8",
+	"sdhi2_ctrl",
+	"sdhi2_cd_a",
+	"sdhi2_wp_a",
+	"sdhi2_cd_b",
+	"sdhi2_wp_b",
+	"sdhi2_ds",
+};
+
+static const char * const sdhi3_groups[] = {
+	"sdhi3_data1",
+	"sdhi3_data4",
+	"sdhi3_data8",
+	"sdhi3_ctrl",
+	"sdhi3_cd",
+	"sdhi3_wp",
+	"sdhi3_ds",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(avb),
 	SH_PFC_FUNCTION(intc_ex),
@@ -2096,6 +2418,10 @@ enum {
 	SH_PFC_FUNCTION(usb0),
 	SH_PFC_FUNCTION(usb1),
 	SH_PFC_FUNCTION(usb30),
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(sdhi3),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.9.1

[PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Yoshihiro Kaneko]

From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>

This patch adds r8a77965 support in SDHI.

Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
 Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
 drivers/mmc/host/renesas_sdhi_internal_dmac.c      | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index ba38252..ee978c9 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -26,6 +26,7 @@ Required properties:
 		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
 		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
 		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
+		"renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
 		"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
 		"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
 		"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index a6bf123..733ea8e 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -99,6 +99,7 @@
 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
 	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
 	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
+	{ .compatible = "renesas,sdhi-r8a77965", .data = &of_rcar_gen3_compatible, },
 	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
 	{},
 };
@@ -276,6 +277,7 @@ static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
 	/* generic ones */
 	{ .soc_id = "r8a7795" },
 	{ .soc_id = "r8a7796" },
+	{ .soc_id = "r8a77965", .revision = "ES1.0" },
 	{ .soc_id = "r8a77980" },
 	{ .soc_id = "r8a77995" },
 	{ /* sentinel */ }
-- 
1.9.1

[PATCH/RFT 3/3] arm64: dts: r8a77965: Add SDHI device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Add SDHI nodes to the DT of the r8a77965 SoC.

Based on several similar patches of the R8A7796 device tree
by Simon Horman <horms+renesas@verge.net.au>.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 68 ++++++++++++++++++++++---------
 1 file changed, 48 insertions(+), 20 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index f0871fc..6860704 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -834,26 +834,6 @@
 			};
 		};
 
-		sdhi0: sd@ee100000 {
-			reg = <0 0xee100000 0 0x2000>;
-			/* placeholder */
-		};
-
-		sdhi1: sd@ee120000 {
-			reg = <0 0xee120000 0 0x2000>;
-			/* placeholder */
-		};
-
-		sdhi2: sd@ee140000 {
-			reg = <0 0xee140000 0 0x2000>;
-			/* placeholder */
-		};
-
-		sdhi3: sd@ee160000 {
-			reg = <0 0xee160000 0 0x2000>;
-			/* placeholder */
-		};
-
 		usb3_phy0: usb-phy@e65ee000 {
 			reg = <0 0xe65ee000 0 0x90>;
 			#phy-cells = <0>;
@@ -874,5 +854,53 @@
 			reg = <0 0xe6020000 0 0x0c>;
 			/* placeholder */
 		};
+
+		sdhi0: sd@ee100000 {
+			compatible = "renesas,sdhi-r8a77965",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee100000 0 0x2000>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 314>;
+			status = "disabled";
+		};
+
+		sdhi1: sd@ee120000 {
+			compatible = "renesas,sdhi-r8a77965",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee120000 0 0x2000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 313>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 313>;
+			status = "disabled";
+		};
+
+		sdhi2: sd@ee140000 {
+			compatible = "renesas,sdhi-r8a77965",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee140000 0 0x2000>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 312>;
+			status = "disabled";
+		};
+
+		sdhi3: sd@ee160000 {
+			compatible = "renesas,sdhi-r8a77965",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee160000 0 0x2000>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 311>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.9.1

Re: [PATCH/RFT 0/3] mmc: renesas_sdhi: add support for r8a77965

[Simon Horman]

On Mon, Apr 30, 2018 at 04:48:13AM +0900, Yoshihiro Kaneko wrote:
> This series adds SDHI device support for r8a77965.
> 
> This series is based on the next branch of Ulf Hansson's mmc tree.
> 
> Masaharu Hayakawa (1):
>   mmc: renesas_sdhi: Add r8a77965 support
> 
> Takeshi Kihara (2):
>   pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

Thanks,

I did some testing of these patches applied on top of a merge of:
* renesas-devel-20180430-v4.17-rc3
* mmc/next (5bec8e5878e2)

And things seem to work :)

Tested-by: Simon Horman <horms+renesas@verge.net.au>



# dmesg | grep mmc
[    1.519354] renesas_sdhi_internal_dmac ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[    1.726791] mmc0: new HS200 MMC card at address 0001
[    1.732769] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB 
[    1.737725] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[    1.744019] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[    1.750462] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)
[    1.879912] renesas_sdhi_internal_dmac ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[    1.949727] renesas_sdhi_internal_dmac ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[    2.055805] mmc1: new ultra high speed SDR50 SDHC card at address e624
[    2.064320] mmcblk1: mmc1:e624 SU08G 7.40 GiB 
[    2.119395] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    2.126544] mmcblk2: mmc2:0001 00000 29.8 GiB 
# dmesg | egrep '(mmc|sd)'
[    1.457672] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[    1.463699] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[    1.519354] renesas_sdhi_internal_dmac ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[    1.529021] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[    1.535111] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[    1.726791] mmc0: new HS200 MMC card at address 0001
[    1.732769] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB 
[    1.737725] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[    1.744019] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[    1.750462] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev (243:0)
[    1.818520] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[    1.824539] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[    1.879912] renesas_sdhi_internal_dmac ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[    1.889678] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[    1.895692] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[    1.949727] renesas_sdhi_internal_dmac ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[    2.055805] mmc1: new ultra high speed SDR50 SDHC card at address e624
[    2.064320] mmcblk1: mmc1:e624 SU08G 7.40 GiB 
[    2.119395] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    2.126544] mmcblk2: mmc2:0001 00000 29.8 GiB 
# time dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2048
[   92.910712] random: crng init done
2048+0 records in
2048+0 records out
real    0m 12.90s
user    0m 0.00s
sys     0m 4.19s
# time dd if=/dev/mmcblk1 of=/dev/null bs=1M count=512
512+0 records in
512+0 records out
real    0m 11.61s
user    0m 0.00s
sys     0m 1.06s
# time dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512
512+0 records in
512+0 records out
real    0m 11.67s
user    0m 0.00s
sys     0m 1.06s
# time dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=512
512+0 records in
512+0 records out
real    0m 21.41s
user    0m 0.00s
sys     0m 2.87s
# time dd if=/dev/zero of=/dev/mmcblk1 bs=1M count=64
64+0 records in
64+0 records out
real    0m 18.07s
user    0m 0.00s
sys     0m 0.43s
# time dd if=/dev/zero of=/dev/mmcblk2 bs=1M count=64
64+0 records in
64+0 records out
real    0m 16.58s
user    0m 0.00s
sys     0m 0.44s

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Simon Horman]

On Mon, Apr 30, 2018 at 04:48:14AM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
> SoC.
> 
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 326 ++++++++++++++++++++++++++++++++++
>  1 file changed, 326 insertions(+)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> index cea9d05..0350197 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> @@ -1923,6 +1923,264 @@ enum {
>  	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
>  };
>  
> +/* - SDHI0 ------------------------------------------------------------------ */
> +static const unsigned int sdhi0_data1_pins[] = {
> +	/* D0 */
> +	RCAR_GP_PIN(3, 2),
> +};
> +
> +static const unsigned int sdhi0_data1_mux[] = {
> +	SD0_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi0_data4_pins[] = {
> +	/* D[0:3] */
> +	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
> +	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
> +};
> +
> +static const unsigned int sdhi0_data4_mux[] = {
> +	SD0_DAT0_MARK, SD0_DAT1_MARK,
> +	SD0_DAT2_MARK, SD0_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi0_ctrl_pins[] = {
> +	/* CLK, CMD */
> +	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> +};
> +
> +static const unsigned int sdhi0_ctrl_mux[] = {
> +	SD0_CLK_MARK, SD0_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi0_cd_pins[] = {
> +	/* CD */
> +	RCAR_GP_PIN(3, 12),
> +};
> +
> +static const unsigned int sdhi0_cd_mux[] = {
> +	SD0_CD_MARK,
> +};
> +
> +static const unsigned int sdhi0_wp_pins[] = {
> +	/* WP */
> +	RCAR_GP_PIN(3, 13),
> +};
> +
> +static const unsigned int sdhi0_wp_mux[] = {
> +	SD0_WP_MARK,
> +};
> +
> +/* - SDHI1 ------------------------------------------------------------------ */
> +static const unsigned int sdhi1_data1_pins[] = {
> +	/* D0 */
> +	RCAR_GP_PIN(3, 8),
> +};
> +
> +static const unsigned int sdhi1_data1_mux[] = {
> +	SD1_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi1_data4_pins[] = {
> +	/* D[0:3] */
> +	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
> +	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
> +};
> +
> +static const unsigned int sdhi1_data4_mux[] = {
> +	SD1_DAT0_MARK, SD1_DAT1_MARK,
> +	SD1_DAT2_MARK, SD1_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi1_ctrl_pins[] = {
> +	/* CLK, CMD */
> +	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
> +};
> +
> +static const unsigned int sdhi1_ctrl_mux[] = {
> +	SD1_CLK_MARK, SD1_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi1_cd_pins[] = {
> +	/* CD */
> +	RCAR_GP_PIN(3, 14),
> +};
> +
> +static const unsigned int sdhi1_cd_mux[] = {
> +	SD1_CD_MARK,
> +};
> +
> +static const unsigned int sdhi1_wp_pins[] = {
> +	/* WP */
> +	RCAR_GP_PIN(3, 15),
> +};
> +
> +static const unsigned int sdhi1_wp_mux[] = {
> +	SD1_WP_MARK,
> +};
> +
> +/* - SDHI2 ------------------------------------------------------------------ */
> +static const unsigned int sdhi2_data1_pins[] = {
> +	/* D0 */
> +	RCAR_GP_PIN(4, 2),
> +};
> +
> +static const unsigned int sdhi2_data1_mux[] = {
> +	SD2_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi2_data4_pins[] = {
> +	/* D[0:3] */
> +	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
> +	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
> +};
> +
> +static const unsigned int sdhi2_data4_mux[] = {
> +	SD2_DAT0_MARK, SD2_DAT1_MARK,
> +	SD2_DAT2_MARK, SD2_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi2_data8_pins[] = {
> +	/* D[0:7] */
> +	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
> +	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
> +	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
> +	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
> +};
> +
> +static const unsigned int sdhi2_data8_mux[] = {
> +	SD2_DAT0_MARK, SD2_DAT1_MARK,
> +	SD2_DAT2_MARK, SD2_DAT3_MARK,
> +	SD2_DAT4_MARK, SD2_DAT5_MARK,
> +	SD2_DAT6_MARK, SD2_DAT7_MARK,
> +};
> +
> +static const unsigned int sdhi2_ctrl_pins[] = {
> +	/* CLK, CMD */
> +	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
> +};
> +
> +static const unsigned int sdhi2_ctrl_mux[] = {
> +	SD2_CLK_MARK, SD2_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi2_cd_a_pins[] = {
> +	/* CD */
> +	RCAR_GP_PIN(4, 13),
> +};
> +
> +static const unsigned int sdhi2_cd_a_mux[] = {
> +	SD2_CD_A_MARK,
> +};
> +
> +static const unsigned int sdhi2_cd_b_pins[] = {
> +	/* CD */
> +	RCAR_GP_PIN(5, 10),
> +};
> +
> +static const unsigned int sdhi2_cd_b_mux[] = {
> +	SD2_CD_B_MARK,
> +};
> +
> +static const unsigned int sdhi2_wp_a_pins[] = {
> +	/* WP */
> +	RCAR_GP_PIN(4, 14),
> +};
> +
> +static const unsigned int sdhi2_wp_a_mux[] = {
> +	SD2_WP_A_MARK,
> +};
> +
> +static const unsigned int sdhi2_wp_b_pins[] = {
> +	/* WP */
> +	RCAR_GP_PIN(5, 11),
> +};
> +
> +static const unsigned int sdhi2_wp_b_mux[] = {
> +	SD2_WP_B_MARK,
> +};
> +
> +static const unsigned int sdhi2_ds_pins[] = {
> +	/* DS */
> +	RCAR_GP_PIN(4, 6),
> +};
> +
> +static const unsigned int sdhi2_ds_mux[] = {
> +	SD2_DS_MARK,
> +};
> +
> +/* - SDHI3 ------------------------------------------------------------------ */
> +static const unsigned int sdhi3_data1_pins[] = {
> +	/* D0 */
> +	RCAR_GP_PIN(4, 9),
> +};
> +
> +static const unsigned int sdhi3_data1_mux[] = {
> +	SD3_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi3_data4_pins[] = {
> +	/* D[0:3] */
> +	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
> +	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
> +};
> +
> +static const unsigned int sdhi3_data4_mux[] = {
> +	SD3_DAT0_MARK, SD3_DAT1_MARK,
> +	SD3_DAT2_MARK, SD3_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi3_data8_pins[] = {
> +	/* D[0:7] */
> +	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
> +	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
> +	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
> +	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
> +};
> +
> +static const unsigned int sdhi3_data8_mux[] = {
> +	SD3_DAT0_MARK, SD3_DAT1_MARK,
> +	SD3_DAT2_MARK, SD3_DAT3_MARK,
> +	SD3_DAT4_MARK, SD3_DAT5_MARK,
> +	SD3_DAT6_MARK, SD3_DAT7_MARK,
> +};
> +
> +static const unsigned int sdhi3_ctrl_pins[] = {
> +	/* CLK, CMD */
> +	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
> +};
> +
> +static const unsigned int sdhi3_ctrl_mux[] = {
> +	SD3_CLK_MARK, SD3_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi3_cd_pins[] = {
> +	/* CD */
> +	RCAR_GP_PIN(4, 15),
> +};
> +
> +static const unsigned int sdhi3_cd_mux[] = {
> +	SD3_CD_MARK,
> +};
> +
> +static const unsigned int sdhi3_wp_pins[] = {
> +	/* WP */
> +	RCAR_GP_PIN(4, 16),
> +};
> +
> +static const unsigned int sdhi3_wp_mux[] = {
> +	SD3_WP_MARK,
> +};
> +
> +static const unsigned int sdhi3_ds_pins[] = {
> +	/* DS */
> +	RCAR_GP_PIN(4, 17),
> +};
> +
> +static const unsigned int sdhi3_ds_mux[] = {
> +	SD3_DS_MARK,
> +};
> +
>  static const unsigned int usb0_mux[] = {
>  	USB0_PWEN_MARK, USB0_OVC_MARK,
>  };
> @@ -1997,6 +2255,32 @@ enum {
>  	SH_PFC_PIN_GROUP(usb0),
>  	SH_PFC_PIN_GROUP(usb1),
>  	SH_PFC_PIN_GROUP(usb30),
> +	SH_PFC_PIN_GROUP(sdhi0_data1),
> +	SH_PFC_PIN_GROUP(sdhi0_data4),
> +	SH_PFC_PIN_GROUP(sdhi0_ctrl),
> +	SH_PFC_PIN_GROUP(sdhi0_cd),
> +	SH_PFC_PIN_GROUP(sdhi0_wp),
> +	SH_PFC_PIN_GROUP(sdhi1_data1),
> +	SH_PFC_PIN_GROUP(sdhi1_data4),
> +	SH_PFC_PIN_GROUP(sdhi1_ctrl),
> +	SH_PFC_PIN_GROUP(sdhi1_cd),
> +	SH_PFC_PIN_GROUP(sdhi1_wp),
> +	SH_PFC_PIN_GROUP(sdhi2_data1),
> +	SH_PFC_PIN_GROUP(sdhi2_data4),
> +	SH_PFC_PIN_GROUP(sdhi2_data8),
> +	SH_PFC_PIN_GROUP(sdhi2_ctrl),
> +	SH_PFC_PIN_GROUP(sdhi2_cd_a),
> +	SH_PFC_PIN_GROUP(sdhi2_wp_a),
> +	SH_PFC_PIN_GROUP(sdhi2_cd_b),
> +	SH_PFC_PIN_GROUP(sdhi2_wp_b),
> +	SH_PFC_PIN_GROUP(sdhi2_ds),
> +	SH_PFC_PIN_GROUP(sdhi3_data1),
> +	SH_PFC_PIN_GROUP(sdhi3_data4),
> +	SH_PFC_PIN_GROUP(sdhi3_data8),
> +	SH_PFC_PIN_GROUP(sdhi3_ctrl),
> +	SH_PFC_PIN_GROUP(sdhi3_cd),
> +	SH_PFC_PIN_GROUP(sdhi3_wp),
> +	SH_PFC_PIN_GROUP(sdhi3_ds),
>  };
>  
>  static const char * const avb_groups[] = {
> @@ -2083,6 +2367,44 @@ enum {
>  	"usb30",
>  };
>  
> +static const char * const sdhi0_groups[] = {
> +	"sdhi0_data1",
> +	"sdhi0_data4",
> +	"sdhi0_ctrl",
> +	"sdhi0_cd",
> +	"sdhi0_wp",
> +};
> +
> +static const char * const sdhi1_groups[] = {
> +	"sdhi1_data1",
> +	"sdhi1_data4",
> +	"sdhi1_ctrl",
> +	"sdhi1_cd",
> +	"sdhi1_wp",
> +};
> +
> +static const char * const sdhi2_groups[] = {
> +	"sdhi2_data1",
> +	"sdhi2_data4",
> +	"sdhi2_data8",
> +	"sdhi2_ctrl",
> +	"sdhi2_cd_a",
> +	"sdhi2_wp_a",
> +	"sdhi2_cd_b",
> +	"sdhi2_wp_b",
> +	"sdhi2_ds",
> +};
> +
> +static const char * const sdhi3_groups[] = {
> +	"sdhi3_data1",
> +	"sdhi3_data4",
> +	"sdhi3_data8",
> +	"sdhi3_ctrl",
> +	"sdhi3_cd",
> +	"sdhi3_wp",
> +	"sdhi3_ds",
> +};
> +
>  static const struct sh_pfc_function pinmux_functions[] = {
>  	SH_PFC_FUNCTION(avb),
>  	SH_PFC_FUNCTION(intc_ex),
> @@ -2096,6 +2418,10 @@ enum {
>  	SH_PFC_FUNCTION(usb0),
>  	SH_PFC_FUNCTION(usb1),
>  	SH_PFC_FUNCTION(usb30),
> +	SH_PFC_FUNCTION(sdhi0),
> +	SH_PFC_FUNCTION(sdhi1),
> +	SH_PFC_FUNCTION(sdhi2),
> +	SH_PFC_FUNCTION(sdhi3),
>  };
>  
>  static const struct pinmux_cfg_reg pinmux_config_regs[] = {
> -- 
> 1.9.1
> 

Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Simon Horman]

On Mon, Apr 30, 2018 at 04:48:15AM +0900, Yoshihiro Kaneko wrote:
> From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
> 
> This patch adds r8a77965 support in SDHI.
> 
> Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> ---
>  Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c      | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> index ba38252..ee978c9 100644
> --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> @@ -26,6 +26,7 @@ Required properties:
>  		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
>  		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
>  		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
> +		"renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
>  		"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
>  		"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
>  		"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
> diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> index a6bf123..733ea8e 100644
> --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> @@ -99,6 +99,7 @@
>  static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
>  	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
>  	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
> +	{ .compatible = "renesas,sdhi-r8a77965", .data = &of_rcar_gen3_compatible, },
>  	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
>  	{},
>  };
> @@ -276,6 +277,7 @@ static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
>  	/* generic ones */
>  	{ .soc_id = "r8a7795" },
>  	{ .soc_id = "r8a7796" },
> +	{ .soc_id = "r8a77965", .revision = "ES1.0" },

I think we can drop .revision = "ES1.0"

to be in keeping with 349936fcdaf8 ("mmc: renesas_sdhi_internal_dmac: use
more generic whitelisting").

With that fixed:

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>


>  	{ .soc_id = "r8a77980" },
>  	{ .soc_id = "r8a77995" },
>  	{ /* sentinel */ }
> -- 
> 1.9.1
> 

Re: [PATCH/RFT 3/3] arm64: dts: r8a77965: Add SDHI device nodes

[Simon Horman]

On Mon, Apr 30, 2018 at 04:48:16AM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> Add SDHI nodes to the DT of the r8a77965 SoC.
> 
> Based on several similar patches of the R8A7796 device tree
> by Simon Horman <horms+renesas@verge.net.au>.
> 
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>

This patch needs to be rebased on top of the devel branch of the renesas
tree. Otherwise it looks good to me.

> ---
>  arch/arm64/boot/dts/renesas/r8a77965.dtsi | 68 ++++++++++++++++++++++---------
>  1 file changed, 48 insertions(+), 20 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> index f0871fc..6860704 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> @@ -834,26 +834,6 @@
>  			};
>  		};
>  
> -		sdhi0: sd@ee100000 {
> -			reg = <0 0xee100000 0 0x2000>;
> -			/* placeholder */
> -		};
> -
> -		sdhi1: sd@ee120000 {
> -			reg = <0 0xee120000 0 0x2000>;
> -			/* placeholder */
> -		};
> -
> -		sdhi2: sd@ee140000 {
> -			reg = <0 0xee140000 0 0x2000>;
> -			/* placeholder */
> -		};
> -
> -		sdhi3: sd@ee160000 {
> -			reg = <0 0xee160000 0 0x2000>;
> -			/* placeholder */
> -		};
> -
>  		usb3_phy0: usb-phy@e65ee000 {
>  			reg = <0 0xe65ee000 0 0x90>;
>  			#phy-cells = <0>;
> @@ -874,5 +854,53 @@
>  			reg = <0 0xe6020000 0 0x0c>;
>  			/* placeholder */
>  		};
> +
> +		sdhi0: sd@ee100000 {
> +			compatible = "renesas,sdhi-r8a77965",
> +				     "renesas,rcar-gen3-sdhi";
> +			reg = <0 0xee100000 0 0x2000>;
> +			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 314>;
> +			max-frequency = <200000000>;
> +			power-domains = <&sysc 32>;
> +			resets = <&cpg 314>;
> +			status = "disabled";
> +		};
> +
> +		sdhi1: sd@ee120000 {
> +			compatible = "renesas,sdhi-r8a77965",
> +				     "renesas,rcar-gen3-sdhi";
> +			reg = <0 0xee120000 0 0x2000>;
> +			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 313>;
> +			max-frequency = <200000000>;
> +			power-domains = <&sysc 32>;
> +			resets = <&cpg 313>;
> +			status = "disabled";
> +		};
> +
> +		sdhi2: sd@ee140000 {
> +			compatible = "renesas,sdhi-r8a77965",
> +				     "renesas,rcar-gen3-sdhi";
> +			reg = <0 0xee140000 0 0x2000>;
> +			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 312>;
> +			max-frequency = <200000000>;
> +			power-domains = <&sysc 32>;
> +			resets = <&cpg 312>;
> +			status = "disabled";
> +		};
> +
> +		sdhi3: sd@ee160000 {
> +			compatible = "renesas,sdhi-r8a77965",
> +				     "renesas,rcar-gen3-sdhi";
> +			reg = <0 0xee160000 0 0x2000>;
> +			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 311>;
> +			max-frequency = <200000000>;
> +			power-domains = <&sysc 32>;
> +			resets = <&cpg 311>;
> +			status = "disabled";
> +		};
>  	};
>  };
> -- 
> 1.9.1
> 

Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Wolfram Sang]

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> > +	{ .compatible = "renesas,sdhi-r8a77965", .data = &of_rcar_gen3_compatible, },

Do we need this line...

> >  	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },

... with this generic fallback in place?

> > @@ -276,6 +277,7 @@ static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
> >  	/* generic ones */
> >  	{ .soc_id = "r8a7795" },
> >  	{ .soc_id = "r8a7796" },
> > +	{ .soc_id = "r8a77965", .revision = "ES1.0" },
> 
> I think we can drop .revision = "ES1.0"
> 
> to be in keeping with 349936fcdaf8 ("mmc: renesas_sdhi_internal_dmac: use
> more generic whitelisting").

Ack.


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Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Simon Horman]

On Wed, May 02, 2018 at 07:32:19AM +0200, Wolfram Sang wrote:
> 
> > > +	{ .compatible = "renesas,sdhi-r8a77965", .data = &of_rcar_gen3_compatible, },
> 
> Do we need this line...
> 
> > >  	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
> 
> ... with this generic fallback in place?

Sorry, I missed that in my review.
I agree that the renesas,sdhi-r8a77965 is not needed.

> 
> > > @@ -276,6 +277,7 @@ static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
> > >  	/* generic ones */
> > >  	{ .soc_id = "r8a7795" },
> > >  	{ .soc_id = "r8a7796" },
> > > +	{ .soc_id = "r8a77965", .revision = "ES1.0" },
> > 
> > I think we can drop .revision = "ES1.0"
> > 
> > to be in keeping with 349936fcdaf8 ("mmc: renesas_sdhi_internal_dmac: use
> > more generic whitelisting").
> 
> Ack.

One more consideration.

With the current state of the driver this patch should be fine,
modulo the changes suggested above. But once HS400 support is merged
some logic will be required to disable that feature for the r8a77965
until HS400 support for that SoC is explicitly added.

Or conversely, perhaps when HS400 is added it should only be enabled
in the driver for SoCs that are known to work: r8a7796 and r8a7795. In the
case of the latter perhaps only ES2.0.

Wolfram, what do you think?

Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Wolfram Sang]

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> With the current state of the driver this patch should be fine,
> modulo the changes suggested above. But once HS400 support is merged
> some logic will be required to disable that feature for the r8a77965
> until HS400 support for that SoC is explicitly added.
> 
> Or conversely, perhaps when HS400 is added it should only be enabled
> in the driver for SoCs that are known to work: r8a7796 and r8a7795. In the
> case of the latter perhaps only ES2.0.
> 
> Wolfram, what do you think?

M3-N (and future SoCs as it seems) has 8 taps while the others have 4.
Maybe we should have something already in place to distinguish 8 taps
and 4 taps and leave the 8 taps part for "to be added later"?


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Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Geert Uytterhoeven]

Hi Kaneko-san,

On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
> SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>

Thanks for your patch!

The pins, groups, and functions are correct, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>.
i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> @@ -1923,6 +1923,264 @@ enum {
>         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
>  };
>
> +/* - SDHI0 ------------------------------------------------------------------ */
> +static const unsigned int sdhi0_data1_pins[] = {

[...]

> +};

This doesn't belong in the middle of the usb0 section ;-)

> +
>  static const unsigned int usb0_mux[] = {
>         USB0_PWEN_MARK, USB0_OVC_MARK,
>  };
> @@ -1997,6 +2255,32 @@ enum {
>         SH_PFC_PIN_GROUP(usb0),
>         SH_PFC_PIN_GROUP(usb1),
>         SH_PFC_PIN_GROUP(usb30),
> +       SH_PFC_PIN_GROUP(sdhi0_data1),

Alphabetical order, please.

> @@ -2083,6 +2367,44 @@ enum {
>         "usb30",
>  };
>
> +static const char * const sdhi0_groups[] = {

Alphabetical order, please.

> @@ -2096,6 +2418,10 @@ enum {
>         SH_PFC_FUNCTION(usb0),
>         SH_PFC_FUNCTION(usb1),
>         SH_PFC_FUNCTION(usb30),
> +       SH_PFC_FUNCTION(sdhi0),
> +       SH_PFC_FUNCTION(sdhi1),
> +       SH_PFC_FUNCTION(sdhi2),
> +       SH_PFC_FUNCTION(sdhi3),
>  };

Alphabetical order, please.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Yoshihiro Kaneko]

Hi Geert-san,

2018-05-02 18:16 GMT+09:00 Geert Uytterhoeven <geert@linux-m68k.org>:
> Hi Kaneko-san,
>
> On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>
>> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
>> SoC.
>>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>
> Thanks for your patch!
>
> The pins, groups, and functions are correct, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>.
> i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.

Thanks for your review!
I will fix up the below in V2.

>
>> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
>> @@ -1923,6 +1923,264 @@ enum {
>>         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
>>  };
>>
>> +/* - SDHI0 ------------------------------------------------------------------ */
>> +static const unsigned int sdhi0_data1_pins[] = {
>
> [...]
>
>> +};
>
> This doesn't belong in the middle of the usb0 section ;-)
>
>> +
>>  static const unsigned int usb0_mux[] = {
>>         USB0_PWEN_MARK, USB0_OVC_MARK,
>>  };
>> @@ -1997,6 +2255,32 @@ enum {
>>         SH_PFC_PIN_GROUP(usb0),
>>         SH_PFC_PIN_GROUP(usb1),
>>         SH_PFC_PIN_GROUP(usb30),
>> +       SH_PFC_PIN_GROUP(sdhi0_data1),
>
> Alphabetical order, please.
>
>> @@ -2083,6 +2367,44 @@ enum {
>>         "usb30",
>>  };
>>
>> +static const char * const sdhi0_groups[] = {
>
> Alphabetical order, please.
>
>> @@ -2096,6 +2418,10 @@ enum {
>>         SH_PFC_FUNCTION(usb0),
>>         SH_PFC_FUNCTION(usb1),
>>         SH_PFC_FUNCTION(usb30),
>> +       SH_PFC_FUNCTION(sdhi0),
>> +       SH_PFC_FUNCTION(sdhi1),
>> +       SH_PFC_FUNCTION(sdhi2),
>> +       SH_PFC_FUNCTION(sdhi3),
>>  };
>
> Alphabetical order, please.
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Best regards,
Kaneko

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Geert Uytterhoeven]

Hi Kaneko-san,

On Fri, May 4, 2018 at 10:28 AM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
> 2018-05-02 18:16 GMT+09:00 Geert Uytterhoeven <geert@linux-m68k.org>:
>> On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
>>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>>
>>> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
>>> SoC.
>>>
>>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>>
>> Thanks for your patch!
>>
>> The pins, groups, and functions are correct, so
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>.
>> i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.
>
> Thanks for your review!
> I will fix up the below in V2.

There's no need to send a v2, as I have already fixed and applied your patch.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Yoshihiro Kaneko]

Hello,

2018-05-02 17:14 GMT+09:00 Wolfram Sang <wsa@the-dreams.de>:
>
>> With the current state of the driver this patch should be fine,
>> modulo the changes suggested above. But once HS400 support is merged
>> some logic will be required to disable that feature for the r8a77965
>> until HS400 support for that SoC is explicitly added.
>>
>> Or conversely, perhaps when HS400 is added it should only be enabled
>> in the driver for SoCs that are known to work: r8a7796 and r8a7795. In the
>> case of the latter perhaps only ES2.0.
>>
>> Wolfram, what do you think?
>
> M3-N (and future SoCs as it seems) has 8 taps while the others have 4.
> Maybe we should have something already in place to distinguish 8 taps
> and 4 taps and leave the 8 taps part for "to be added later"?
>

Thanks for your review.
I will drop .revision = "ES1.0" and renesas,sdhi-r8a77965 in V2.

Best regards,
Kaneko

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Yoshihiro Kaneko]

Hi Geert-san,

2018-05-04 17:30 GMT+09:00 Geert Uytterhoeven <geert@linux-m68k.org>:
> Hi Kaneko-san,
>
> On Fri, May 4, 2018 at 10:28 AM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
>> 2018-05-02 18:16 GMT+09:00 Geert Uytterhoeven <geert@linux-m68k.org>:
>>> On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
>>>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>>>
>>>> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
>>>> SoC.
>>>>
>>>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>>> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>>>
>>> Thanks for your patch!
>>>
>>> The pins, groups, and functions are correct, so
>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>.
>>> i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.
>>
>> Thanks for your review!
>> I will fix up the below in V2.
>
> There's no need to send a v2, as I have already fixed and applied your patch.

Okay, Thanks!

>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH/RFT 3/3] arm64: dts: r8a77965: Add SDHI device nodes

[Yoshihiro Kaneko]

Hi Simon-san,

2018-05-02 0:30 GMT+09:00 Simon Horman <horms@verge.net.au>:
> On Mon, Apr 30, 2018 at 04:48:16AM +0900, Yoshihiro Kaneko wrote:
>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>
>> Add SDHI nodes to the DT of the r8a77965 SoC.
>>
>> Based on several similar patches of the R8A7796 device tree
>> by Simon Horman <horms+renesas@verge.net.au>.
>>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>
> This patch needs to be rebased on top of the devel branch of the renesas
> tree. Otherwise it looks good to me.

Thanks for your review.
I will rebase this patch.

>
>> ---
>>  arch/arm64/boot/dts/renesas/r8a77965.dtsi | 68 ++++++++++++++++++++++---------
>>  1 file changed, 48 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
>> index f0871fc..6860704 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
>> @@ -834,26 +834,6 @@
>>                       };
>>               };
>>
>> -             sdhi0: sd@ee100000 {
>> -                     reg = <0 0xee100000 0 0x2000>;
>> -                     /* placeholder */
>> -             };
>> -
>> -             sdhi1: sd@ee120000 {
>> -                     reg = <0 0xee120000 0 0x2000>;
>> -                     /* placeholder */
>> -             };
>> -
>> -             sdhi2: sd@ee140000 {
>> -                     reg = <0 0xee140000 0 0x2000>;
>> -                     /* placeholder */
>> -             };
>> -
>> -             sdhi3: sd@ee160000 {
>> -                     reg = <0 0xee160000 0 0x2000>;
>> -                     /* placeholder */
>> -             };
>> -
>>               usb3_phy0: usb-phy@e65ee000 {
>>                       reg = <0 0xe65ee000 0 0x90>;
>>                       #phy-cells = <0>;
>> @@ -874,5 +854,53 @@
>>                       reg = <0 0xe6020000 0 0x0c>;
>>                       /* placeholder */
>>               };
>> +
>> +             sdhi0: sd@ee100000 {
>> +                     compatible = "renesas,sdhi-r8a77965",
>> +                                  "renesas,rcar-gen3-sdhi";
>> +                     reg = <0 0xee100000 0 0x2000>;
>> +                     interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&cpg CPG_MOD 314>;
>> +                     max-frequency = <200000000>;
>> +                     power-domains = <&sysc 32>;
>> +                     resets = <&cpg 314>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             sdhi1: sd@ee120000 {
>> +                     compatible = "renesas,sdhi-r8a77965",
>> +                                  "renesas,rcar-gen3-sdhi";
>> +                     reg = <0 0xee120000 0 0x2000>;
>> +                     interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&cpg CPG_MOD 313>;
>> +                     max-frequency = <200000000>;
>> +                     power-domains = <&sysc 32>;
>> +                     resets = <&cpg 313>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             sdhi2: sd@ee140000 {
>> +                     compatible = "renesas,sdhi-r8a77965",
>> +                                  "renesas,rcar-gen3-sdhi";
>> +                     reg = <0 0xee140000 0 0x2000>;
>> +                     interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&cpg CPG_MOD 312>;
>> +                     max-frequency = <200000000>;
>> +                     power-domains = <&sysc 32>;
>> +                     resets = <&cpg 312>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             sdhi3: sd@ee160000 {
>> +                     compatible = "renesas,sdhi-r8a77965",
>> +                                  "renesas,rcar-gen3-sdhi";
>> +                     reg = <0 0xee160000 0 0x2000>;
>> +                     interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&cpg CPG_MOD 311>;
>> +                     max-frequency = <200000000>;
>> +                     power-domains = <&sysc 32>;
>> +                     resets = <&cpg 311>;
>> +                     status = "disabled";
>> +             };
>>       };
>>  };
>> --
>> 1.9.1
>>

Best regards,
Kaneko

Re: [PATCH/RFT 0/3] mmc: renesas_sdhi: add support for r8a77965

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 1296 bytes --]

On Tue, May 01, 2018 at 05:27:07PM +0200, Simon Horman wrote:
> On Mon, Apr 30, 2018 at 04:48:13AM +0900, Yoshihiro Kaneko wrote:
> > This series adds SDHI device support for r8a77965.
> > 
> > This series is based on the next branch of Ulf Hansson's mmc tree.
> > 
> > Masaharu Hayakawa (1):
> >   mmc: renesas_sdhi: Add r8a77965 support
> > 
> > Takeshi Kihara (2):
> >   pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions
> 
> Thanks,
> 
> I did some testing of these patches applied on top of a merge of:
> * renesas-devel-20180430-v4.17-rc3
> * mmc/next (5bec8e5878e2)
> 
> And things seem to work :)
> 
> Tested-by: Simon Horman <horms+renesas@verge.net.au>

Same here. Checked with the internal eMMC (the MMC core needs to do some
retries for tuning with HS200 on cold-boot, but then it works. Always
immediately works after warm-boot), and both SDHI slots. Checksumming
files with SDR50 works fine.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> # time dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2048

It may be a little bit more typing but I think it is worth the effort to
catch more bugs: dd'ing a file from /dev/urandom to /tmp, checksum it
and write it to the SD cards, re-read and compare the md5sums?

Thanks all!


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Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Simon Horman]

On Wed, May 02, 2018 at 10:14:15AM +0200, Wolfram Sang wrote:
> 
> > With the current state of the driver this patch should be fine,
> > modulo the changes suggested above. But once HS400 support is merged
> > some logic will be required to disable that feature for the r8a77965
> > until HS400 support for that SoC is explicitly added.
> > 
> > Or conversely, perhaps when HS400 is added it should only be enabled
> > in the driver for SoCs that are known to work: r8a7796 and r8a7795. In the
> > case of the latter perhaps only ES2.0.
> > 
> > Wolfram, what do you think?
> 
> M3-N (and future SoCs as it seems) has 8 taps while the others have 4.
> Maybe we should have something already in place to distinguish 8 taps
> and 4 taps and leave the 8 taps part for "to be added later"?

Yes, that is one option.