[PATCH 1/3] drm/i915: Flush submission tasklet after bumping priority

[PATCH 1/3] drm/i915: Flush submission tasklet after bumping priority

[Chris Wilson]

When called from process context tasklet_schedule() defers itself to
ksoftirqd. From experience this may cause unacceptable latencies of over
200ms in executing the submission tasklet, our goal is to reprioritise
the HW execution queue and trigger preemption immediately, so convert
the rcu protection over to include a kick of the tasklet.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5ece6ae4bdff..03cd30001b5d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -578,10 +578,10 @@ static void __fence_set_priority(struct dma_fence *fence,
 	rq = to_request(fence);
 	engine = rq->engine;
 
-	rcu_read_lock();
+	local_bh_disable(); /* RCU serialisation for set-wedged protection */
 	if (engine->schedule)
 		engine->schedule(rq, attr);
-	rcu_read_unlock();
+	local_bh_enable(); /* kick the tasklets if queues were reprioritised */
 }
 
 static void fence_set_priority(struct dma_fence *fence,
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/3] drm/i915: Combine set-wedged protection and tasklet kicking

[Chris Wilson]

Around request submission, we protect the call to schedule with a
premption disable loop to prevent set-wedge chaning function pointers
underneath us. This also prevents the tasklet running on the local CPU,
a trick we use immediately afterwards to forcibly execute the tasklet
after submission. We can combine the two wlog, and ensure that the
tasklet is only executed (on the local CPU) after we complete our
updates to the submission queue (and not after an intermediate,
incomplete update).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_request.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index e4cf76ec14a6..88ee444679d4 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1110,12 +1110,9 @@ void __i915_request_add(struct i915_request *request, bool flush_caches)
 	 * decide whether to preempt the entire chain so that it is ready to
 	 * run at the earliest possible convenience.
 	 */
-	rcu_read_lock();
+	local_bh_disable();
 	if (engine->schedule)
 		engine->schedule(request, &request->ctx->sched);
-	rcu_read_unlock();
-
-	local_bh_disable();
 	i915_sw_fence_commit(&request->submit);
 	local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
 
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/3] drm/i915/execlists: Direct submit onto idle engines

[Chris Wilson]

Bypass using the tasklet to submit the first request to HW, as the
tasklet may be deferred unto ksoftirqd and at a minimum will add in
excess of 10us (and maybe tens of milliseconds) to our execution
latency. This latency reduction is most notable when execution flows
between engines.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_submission.c |  1 +
 drivers/gpu/drm/i915/intel_lrc.c            | 64 +++++++++++++++++----
 drivers/gpu/drm/i915/intel_ringbuffer.h     |  7 +++
 3 files changed, 60 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 62828e39ee26..d899a2e6fa7d 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1255,6 +1255,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
 		engine->unpark = guc_submission_unpark;
 
 		engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+		engine->flags |= I915_ENGINE_HAS_GUC;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f9f4064dec0e..8a1ed31c4fc3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -554,7 +554,7 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
 	execlists_set_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT);
 }
 
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool __execlists_dequeue(struct intel_engine_cs *engine)
 {
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct execlist_port *port = execlists->port;
@@ -564,6 +564,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	struct rb_node *rb;
 	bool submit = false;
 
+	lockdep_assert_held(&engine->timeline.lock);
+
 	/* Hardware submission is through 2 ports. Conceptually each port
 	 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
 	 * static for a context, and unique to each, so we only execute
@@ -585,7 +587,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	 * and context switches) submission.
 	 */
 
-	spin_lock_irq(&engine->timeline.lock);
 	rb = execlists->first;
 	GEM_BUG_ON(rb_first(&execlists->queue) != rb);
 
@@ -598,6 +599,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 		 */
 		GEM_BUG_ON(!execlists_is_active(execlists,
 						EXECLISTS_ACTIVE_USER));
+		GEM_BUG_ON(execlists_is_active(execlists,
+					       EXECLISTS_ACTIVE_PREEMPT));
 		GEM_BUG_ON(!port_count(&port[0]));
 		if (port_count(&port[0]) > 1)
 			goto unlock;
@@ -745,12 +748,23 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	GEM_BUG_ON(execlists->first && !port_isset(execlists->port));
 
 unlock:
+	if (last)
+		execlists_user_begin(execlists, execlists->port);
+
+	return submit;
+}
+
+static void execlists_dequeue(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlists * const execlists = &engine->execlists;
+	bool submit;
+
+	spin_lock_irq(&engine->timeline.lock);
+	submit = __execlists_dequeue(engine);
 	spin_unlock_irq(&engine->timeline.lock);
 
-	if (submit) {
-		execlists_user_begin(execlists, execlists->port);
+	if (submit)
 		execlists_submit_ports(engine);
-	}
 
 	GEM_BUG_ON(port_isset(execlists->port) &&
 		   !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
@@ -1147,16 +1161,41 @@ static void queue_request(struct intel_engine_cs *engine,
 		      &lookup_priolist(engine, node, prio)->requests);
 }
 
-static void __submit_queue(struct intel_engine_cs *engine, int prio)
+static void __wakeup_queue(struct intel_engine_cs *engine, int prio)
 {
 	engine->execlists.queue_priority = prio;
+}
+
+static void __schedule_queue(struct intel_engine_cs *engine)
+{
 	tasklet_hi_schedule(&engine->execlists.tasklet);
 }
 
+static void __submit_queue(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlists * const execlists = &engine->execlists;
+
+	GEM_BUG_ON(!engine->i915->gt.awake);
+
+	/* Directly submit the first request to reduce the initial latency */
+	if (!intel_engine_has_guc(engine) &&
+	    !port_isset(execlists->port) &&
+	    tasklet_trylock(&execlists->tasklet)) {
+		if (__execlists_dequeue(engine))
+			execlists_submit_ports(engine);
+		tasklet_unlock(&execlists->tasklet);
+		return;
+	}
+
+	__schedule_queue(engine);
+}
+
 static void submit_queue(struct intel_engine_cs *engine, int prio)
 {
-	if (prio > engine->execlists.queue_priority)
-		__submit_queue(engine, prio);
+	if (prio > engine->execlists.queue_priority) {
+		__wakeup_queue(engine, prio);
+		__submit_queue(engine);
+	}
 }
 
 static void execlists_submit_request(struct i915_request *request)
@@ -1168,10 +1207,9 @@ static void execlists_submit_request(struct i915_request *request)
 	spin_lock_irqsave(&engine->timeline.lock, flags);
 
 	queue_request(engine, &request->sched, rq_prio(request));
-	submit_queue(engine, rq_prio(request));
-
 	GEM_BUG_ON(!engine->execlists.first);
 	GEM_BUG_ON(list_empty(&request->sched.link));
+	submit_queue(engine, rq_prio(request));
 
 	spin_unlock_irqrestore(&engine->timeline.lock, flags);
 }
@@ -1293,8 +1331,10 @@ static void execlists_schedule(struct i915_request *request,
 		}
 
 		if (prio > engine->execlists.queue_priority &&
-		    i915_sw_fence_done(&sched_to_request(node)->submit))
-			__submit_queue(engine, prio);
+		    i915_sw_fence_done(&sched_to_request(node)->submit)) {
+			__wakeup_queue(engine, prio);
+			__schedule_queue(engine);
+		}
 	}
 
 	spin_unlock_irq(&engine->timeline.lock);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 010750e8ee44..3d13835d4a87 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -569,6 +569,7 @@ struct intel_engine_cs {
 #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
 #define I915_ENGINE_SUPPORTS_STATS   BIT(1)
 #define I915_ENGINE_HAS_PREEMPTION   BIT(2)
+#define I915_ENGINE_HAS_GUC          BIT(3)
 	unsigned int flags;
 
 	/*
@@ -646,6 +647,12 @@ intel_engine_has_preemption(const struct intel_engine_cs *engine)
 	return engine->flags & I915_ENGINE_HAS_PREEMPTION;
 }
 
+static inline bool
+intel_engine_has_guc(const struct intel_engine_cs *engine)
+{
+	return engine->flags & I915_ENGINE_HAS_GUC;
+}
+
 static inline bool __execlists_need_preempt(int prio, int last)
 {
 	return prio > max(0, last);
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/3] drm/i915/execlists: Direct submit onto idle engines

[Chris Wilson]

Quoting Chris Wilson (2018-05-06 23:47:28)
> +static void __submit_queue(struct intel_engine_cs *engine)
> +{
> +       struct intel_engine_execlists * const execlists = &engine->execlists;
> +
> +       GEM_BUG_ON(!engine->i915->gt.awake);
> +
> +       /* Directly submit the first request to reduce the initial latency */
> +       if (!intel_engine_has_guc(engine) &&
> +           !port_isset(execlists->port) &&
> +           tasklet_trylock(&execlists->tasklet)) {
> +               if (__execlists_dequeue(engine))
> +                       execlists_submit_ports(engine);
> +               tasklet_unlock(&execlists->tasklet);
> +               return;
> +       }
> +
> +       __schedule_queue(engine);
> +}

> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 010750e8ee44..3d13835d4a87 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -569,6 +569,7 @@ struct intel_engine_cs {
>  #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
>  #define I915_ENGINE_SUPPORTS_STATS   BIT(1)
>  #define I915_ENGINE_HAS_PREEMPTION   BIT(2)
> +#define I915_ENGINE_HAS_GUC          BIT(3)

I915_ENGINE_NO_DIRECT_SUBMISSION might be more apt, as I'll want this
bit for virtual engine as well
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority
URL   : https://patchwork.freedesktop.org/series/42783/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f722a94e0311 drm/i915: Flush submission tasklet after bumping priority
dbbfad983f37 drm/i915: Combine set-wedged protection and tasklet kicking
-:7: WARNING:TYPO_SPELLING: 'premption' may be misspelled - perhaps 'preemption'?
#7: 
premption disable loop to prevent set-wedge chaning function pointers

total: 0 errors, 1 warnings, 0 checks, 13 lines checked
bf12b640ec19 drm/i915/execlists: Direct submit onto idle engines

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority
URL   : https://patchwork.freedesktop.org/series/42783/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Flush submission tasklet after bumping priority
Okay!

Commit: drm/i915: Combine set-wedged protection and tasklet kicking
Okay!

Commit: drm/i915/execlists: Direct submit onto idle engines
-O:drivers/gpu/drm/i915/intel_ringbuffer.h:651:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_ringbuffer.h:651:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_ringbuffer.h:658:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_ringbuffer.h:658:23: warning: expression using sizeof(void)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority
URL   : https://patchwork.freedesktop.org/series/42783/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4149 -> Patchwork_8919 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42783/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8919 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-cnl-psr:         PASS -> DMESG-WARN (fdo#104951)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-ivb-3520m:       PASS -> DMESG-WARN (fdo#106084)

    
    ==== Possible fixes ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    igt@gem_exec_suspend@basic-s4-devices:
      fi-skl-guc:         FAIL (fdo#105900, fdo#104699) -> PASS +1

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-cnl-psr:         FAIL (fdo#100368) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      {fi-hsw-peppy}:     DMESG-FAIL (fdo#106103, fdo#102614) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104699 https://bugs.freedesktop.org/show_bug.cgi?id=104699
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (40 -> 36) ==

  Missing    (4): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq fi-pnv-d510 


== Build changes ==

    * Linux: CI_DRM_4149 -> Patchwork_8919

  CI_DRM_4149: 6c2ec0dee7d19b798a1de1101175f5a076549cd9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4461: f772d9a910130b3aec8efa4f09ed723618fae656 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8919: bf12b640ec19fb1b8bdcf0ef3a6422f6658dc0ef @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4461: 55207ea5154dfaa6d2c128124c50e3be4f9b6440 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

bf12b640ec19 drm/i915/execlists: Direct submit onto idle engines
dbbfad983f37 drm/i915: Combine set-wedged protection and tasklet kicking
f722a94e0311 drm/i915: Flush submission tasklet after bumping priority

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8919/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority
URL   : https://patchwork.freedesktop.org/series/42783/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4149_full -> Patchwork_8919_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8919_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8919_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42783/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8919_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@gem_eio@wait-1us:
      shard-kbl:          PASS -> DMESG-FAIL +2
      shard-glk:          PASS -> DMESG-FAIL
      shard-apl:          PASS -> DMESG-FAIL

    igt@gem_ringfill@basic-default-hang:
      shard-kbl:          PASS -> DMESG-WARN +13

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
      shard-apl:          PASS -> FAIL

    igt@kms_vblank@pipe-b-wait-forked-busy-hang:
      shard-glk:          PASS -> DMESG-WARN +7

    igt@kms_vblank@pipe-c-ts-continuation-idle-hang:
      shard-apl:          PASS -> DMESG-WARN +7

    
    ==== Warnings ====

    igt@gem_exec_schedule@preempt-other-bsd1:
      shard-kbl:          PASS -> SKIP +1

    igt@gem_exec_schedule@wide-blt:
      shard-glk:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_8919_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927)
      shard-glk:          PASS -> INCOMPLETE (fdo#103359, k.org#198133)

    igt@gem_eio@execbuf:
      shard-glk:          PASS -> FAIL (fdo#105957) +20

    igt@gem_eio@in-flight-immediate:
      shard-apl:          PASS -> FAIL (fdo#105957) +20

    igt@gem_eio@suspend:
      shard-kbl:          PASS -> FAIL (fdo#105957) +18

    igt@kms_flip@dpms-vs-vblank-race:
      shard-glk:          PASS -> FAIL (fdo#103060)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#102887, fdo#105363)

    igt@kms_vblank@pipe-c-ts-continuation-suspend:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665) +1

    
    ==== Possible fixes ====

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-kbl:          INCOMPLETE (fdo#103665, fdo#106023) -> PASS

    igt@kms_flip@absolute-wf_vblank-interruptible:
      shard-glk:          FAIL (fdo#106087) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@prime_vgem@basic-fence-flip:
      shard-kbl:          DMESG-WARN (fdo#106247) -> PASS

    
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
  fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4149 -> Patchwork_8919

  CI_DRM_4149: 6c2ec0dee7d19b798a1de1101175f5a076549cd9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4461: f772d9a910130b3aec8efa4f09ed723618fae656 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8919: bf12b640ec19fb1b8bdcf0ef3a6422f6658dc0ef @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4461: 55207ea5154dfaa6d2c128124c50e3be4f9b6440 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8919/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2] drm/i915/execlists: Direct submit onto idle engines

[Chris Wilson]

Bypass using the tasklet to submit the first request to HW, as the
tasklet may be deferred unto ksoftirqd and at a minimum will add in
excess of 10us (and maybe tens of milliseconds) to our execution
latency. This latency reduction is most notable when execution flows
between engines.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_submission.c |  7 ++-
 drivers/gpu/drm/i915/intel_lrc.c            | 70 +++++++++++++++++----
 drivers/gpu/drm/i915/intel_ringbuffer.h     |  7 +++
 3 files changed, 69 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 62828e39ee26..bddcf7f13123 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -679,7 +679,9 @@ static void guc_dequeue(struct intel_engine_cs *engine)
 	bool submit = false;
 	struct rb_node *rb;
 
-	spin_lock_irq(&engine->timeline.lock);
+	if (!intel_engine_direct_submit(engine))
+		spin_lock_irq(&engine->timeline.lock);
+
 	rb = execlists->first;
 	GEM_BUG_ON(rb_first(&execlists->queue) != rb);
 
@@ -750,7 +752,8 @@ static void guc_dequeue(struct intel_engine_cs *engine)
 	GEM_BUG_ON(execlists->first && !port_isset(execlists->port));
 
 unlock:
-	spin_unlock_irq(&engine->timeline.lock);
+	if (!intel_engine_direct_submit(engine))
+		spin_unlock_irq(&engine->timeline.lock);
 }
 
 static void guc_submission_tasklet(unsigned long data)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f9f4064dec0e..02789194f33f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -554,7 +554,7 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
 	execlists_set_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT);
 }
 
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool __execlists_dequeue(struct intel_engine_cs *engine)
 {
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct execlist_port *port = execlists->port;
@@ -564,6 +564,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	struct rb_node *rb;
 	bool submit = false;
 
+	lockdep_assert_held(&engine->timeline.lock);
+
 	/* Hardware submission is through 2 ports. Conceptually each port
 	 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
 	 * static for a context, and unique to each, so we only execute
@@ -585,7 +587,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	 * and context switches) submission.
 	 */
 
-	spin_lock_irq(&engine->timeline.lock);
 	rb = execlists->first;
 	GEM_BUG_ON(rb_first(&execlists->queue) != rb);
 
@@ -598,6 +599,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 		 */
 		GEM_BUG_ON(!execlists_is_active(execlists,
 						EXECLISTS_ACTIVE_USER));
+		GEM_BUG_ON(execlists_is_active(execlists,
+					       EXECLISTS_ACTIVE_PREEMPT));
 		GEM_BUG_ON(!port_count(&port[0]));
 		if (port_count(&port[0]) > 1)
 			goto unlock;
@@ -745,12 +748,27 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	GEM_BUG_ON(execlists->first && !port_isset(execlists->port));
 
 unlock:
-	spin_unlock_irq(&engine->timeline.lock);
-
-	if (submit) {
+	if (last)
 		execlists_user_begin(execlists, execlists->port);
+
+	return submit;
+}
+
+static void execlists_dequeue(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlists * const execlists = &engine->execlists;
+	bool submit;
+
+	if (!intel_engine_direct_submit(engine))
+		spin_lock_irq(&engine->timeline.lock);
+
+	submit = __execlists_dequeue(engine);
+
+	if (!intel_engine_direct_submit(engine))
+		spin_unlock_irq(&engine->timeline.lock);
+
+	if (submit)
 		execlists_submit_ports(engine);
-	}
 
 	GEM_BUG_ON(port_isset(execlists->port) &&
 		   !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
@@ -1147,16 +1165,41 @@ static void queue_request(struct intel_engine_cs *engine,
 		      &lookup_priolist(engine, node, prio)->requests);
 }
 
-static void __submit_queue(struct intel_engine_cs *engine, int prio)
+static void __wakeup_queue(struct intel_engine_cs *engine, int prio)
 {
 	engine->execlists.queue_priority = prio;
+}
+
+static void __schedule_queue(struct intel_engine_cs *engine)
+{
 	tasklet_hi_schedule(&engine->execlists.tasklet);
 }
 
+static void __submit_queue(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlists * const execlists = &engine->execlists;
+
+	GEM_BUG_ON(!engine->i915->gt.awake);
+
+	/* Directly submit the first request to reduce the initial latency */
+	if (!port_isset(execlists->port) &&
+	    tasklet_trylock(&execlists->tasklet)) {
+		engine->flags |= I915_ENGINE_DIRECT_SUBMIT;
+		execlists->tasklet.func(execlists->tasklet.data);
+		engine->flags &= ~I915_ENGINE_DIRECT_SUBMIT;
+		tasklet_unlock(&execlists->tasklet);
+		return;
+	}
+
+	__schedule_queue(engine);
+}
+
 static void submit_queue(struct intel_engine_cs *engine, int prio)
 {
-	if (prio > engine->execlists.queue_priority)
-		__submit_queue(engine, prio);
+	if (prio > engine->execlists.queue_priority) {
+		__wakeup_queue(engine, prio);
+		__submit_queue(engine);
+	}
 }
 
 static void execlists_submit_request(struct i915_request *request)
@@ -1168,10 +1211,9 @@ static void execlists_submit_request(struct i915_request *request)
 	spin_lock_irqsave(&engine->timeline.lock, flags);
 
 	queue_request(engine, &request->sched, rq_prio(request));
-	submit_queue(engine, rq_prio(request));
-
 	GEM_BUG_ON(!engine->execlists.first);
 	GEM_BUG_ON(list_empty(&request->sched.link));
+	submit_queue(engine, rq_prio(request));
 
 	spin_unlock_irqrestore(&engine->timeline.lock, flags);
 }
@@ -1293,8 +1335,10 @@ static void execlists_schedule(struct i915_request *request,
 		}
 
 		if (prio > engine->execlists.queue_priority &&
-		    i915_sw_fence_done(&sched_to_request(node)->submit))
-			__submit_queue(engine, prio);
+		    i915_sw_fence_done(&sched_to_request(node)->submit)) {
+			__wakeup_queue(engine, prio);
+			__schedule_queue(engine);
+		}
 	}
 
 	spin_unlock_irq(&engine->timeline.lock);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 010750e8ee44..f5545391d76a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -569,6 +569,7 @@ struct intel_engine_cs {
 #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
 #define I915_ENGINE_SUPPORTS_STATS   BIT(1)
 #define I915_ENGINE_HAS_PREEMPTION   BIT(2)
+#define I915_ENGINE_DIRECT_SUBMIT    BIT(3)
 	unsigned int flags;
 
 	/*
@@ -646,6 +647,12 @@ intel_engine_has_preemption(const struct intel_engine_cs *engine)
 	return engine->flags & I915_ENGINE_HAS_PREEMPTION;
 }
 
+static inline bool
+intel_engine_direct_submit(const struct intel_engine_cs *engine)
+{
+	return engine->flags & I915_ENGINE_DIRECT_SUBMIT;
+}
+
 static inline bool __execlists_need_preempt(int prio, int last)
 {
 	return prio > max(0, last);
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)
URL   : https://patchwork.freedesktop.org/series/42783/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5b9b411b4a48 drm/i915: Flush submission tasklet after bumping priority
7f646ffa9f8b drm/i915: Combine set-wedged protection and tasklet kicking
-:7: WARNING:TYPO_SPELLING: 'premption' may be misspelled - perhaps 'preemption'?
#7: 
premption disable loop to prevent set-wedge chaning function pointers

total: 0 errors, 1 warnings, 0 checks, 13 lines checked
c95a4bf7c4de drm/i915/execlists: Direct submit onto idle engines

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)
URL   : https://patchwork.freedesktop.org/series/42783/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Flush submission tasklet after bumping priority
Okay!

Commit: drm/i915: Combine set-wedged protection and tasklet kicking
Okay!

Commit: drm/i915/execlists: Direct submit onto idle engines
+drivers/gpu/drm/i915/intel_guc_submission.c:756:32: warning: context imbalance in 'guc_dequeue' - unexpected unlock
+drivers/gpu/drm/i915/intel_lrc.c:768:32: warning: context imbalance in 'execlists_dequeue' - unexpected unlock
-O:drivers/gpu/drm/i915/intel_ringbuffer.h:651:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_ringbuffer.h:651:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_ringbuffer.h:658:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_ringbuffer.h:658:23: warning: expression using sizeof(void)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)
URL   : https://patchwork.freedesktop.org/series/42783/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4150 -> Patchwork_8920 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42783/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8920 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload:
      fi-bsw-n3050:       PASS -> DMESG-FAIL (fdo#106373)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-ivb-3520m:       PASS -> DMESG-WARN (fdo#106084)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    
    ==== Possible fixes ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-skl-guc:         FAIL (fdo#103928) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-4200u:       DMESG-FAIL (fdo#102614, fdo#106103) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      fi-skl-6700k2:      FAIL (fdo#103191, fdo#104724) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-glk-j4005:       DMESG-WARN (fdo#106097) -> PASS

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
  fdo#106373 https://bugs.freedesktop.org/show_bug.cgi?id=106373


== Participating hosts (38 -> 35) ==

  Missing    (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4150 -> Patchwork_8920

  CI_DRM_4150: 93d32416ba4b1dae9451fec28aaa71915d770f51 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4463: 91b5a3ef5516b29584ea4567b0f5ffa18219b29f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8920: c95a4bf7c4de6d4281a565ea9927692d40c5a35f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4463: 33e58d5583eb7ed3966a1b905f875a1dfa959f6b @ git://anongit.freedesktop.org/piglit


== Linux commits ==

c95a4bf7c4de drm/i915/execlists: Direct submit onto idle engines
7f646ffa9f8b drm/i915: Combine set-wedged protection and tasklet kicking
5b9b411b4a48 drm/i915: Flush submission tasklet after bumping priority

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8920/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Flush submission tasklet after bumping priority (rev2)
URL   : https://patchwork.freedesktop.org/series/42783/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4150_full -> Patchwork_8920_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8920_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8920_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42783/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8920_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_hangman@error-state-capture-bsd:
      shard-glk:          PASS -> DMESG-WARN +5

    igt@gem_eio@reset-stress:
      shard-glk:          PASS -> DMESG-FAIL +1
      shard-kbl:          PASS -> DMESG-FAIL +1

    igt@gem_eio@wait-immediate:
      shard-apl:          PASS -> DMESG-FAIL

    igt@gem_ringfill@basic-default-hang:
      shard-kbl:          PASS -> DMESG-WARN +13

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
      shard-apl:          PASS -> FAIL +5

    igt@kms_vblank@pipe-b-wait-busy-hang:
      shard-kbl:          PASS -> FAIL +3

    igt@kms_vblank@pipe-c-query-forked-hang:
      shard-apl:          PASS -> DMESG-WARN +6

    igt@pm_rpm@gem-idle:
      shard-glk:          PASS -> FAIL +5

    
    ==== Warnings ====

    igt@gem_exec_schedule@preempt-hang-bsd:
      shard-glk:          PASS -> SKIP +1

    igt@gem_mocs_settings@mocs-rc6-render:
      shard-kbl:          SKIP -> PASS +1

    igt@gem_mocs_settings@mocs-rc6-vebox:
      shard-kbl:          PASS -> SKIP +2

    igt@kms_flip@flip-vs-modeset-vs-hang:
      shard-apl:          PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_8920_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_contexts:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665)

    igt@drv_selftest@live_hangcheck:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927)
      shard-glk:          PASS -> INCOMPLETE (k.org#198133, fdo#103359)

    igt@gem_eio@execbuf:
      shard-glk:          PASS -> FAIL (fdo#105957) +19

    igt@gem_eio@in-flight-immediate:
      shard-apl:          PASS -> FAIL (fdo#105957) +20

    igt@gem_eio@suspend:
      shard-kbl:          PASS -> FAIL (fdo#105957) +18

    igt@kms_flip@absolute-wf_vblank-interruptible:
      shard-apl:          PASS -> FAIL (fdo#106087)

    igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#100368) +1

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#105707)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
      shard-hsw:          PASS -> FAIL (fdo#103481)

    igt@kms_rotation_crc@sprite-rotation-180:
      shard-hsw:          PASS -> FAIL (fdo#104724, fdo#103925) +1

    
    ==== Possible fixes ====

    igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
      shard-kbl:          FAIL (fdo#100368) -> PASS

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          FAIL (fdo#105363) -> PASS

    igt@kms_flip@plain-flip-fb-recreate:
      shard-glk:          FAIL (fdo#100368) -> PASS +2

    igt@kms_frontbuffer_tracking@fbc-farfromfence:
      shard-kbl:          DMESG-WARN (fdo#103558, fdo#105602) -> PASS +12

    igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
      shard-apl:          FAIL (fdo#104724, fdo#103166) -> PASS

    igt@kms_rotation_crc@primary-rotation-90:
      shard-apl:          FAIL (fdo#104724, fdo#103925) -> PASS

    
    ==== Warnings ====

    igt@gem_eio@hibernate:
      shard-kbl:          DMESG-WARN (fdo#103558, fdo#105602) -> FAIL (fdo#105957)

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957
  fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4150 -> Patchwork_8920

  CI_DRM_4150: 93d32416ba4b1dae9451fec28aaa71915d770f51 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4463: 91b5a3ef5516b29584ea4567b0f5ffa18219b29f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8920: c95a4bf7c4de6d4281a565ea9927692d40c5a35f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4463: 33e58d5583eb7ed3966a1b905f875a1dfa959f6b @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8920/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx