From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Date: Mon, 7 May 2018 13:03:24 +0530 Subject: [U-Boot] [PATCH v7 08/35] sunxi: clock: Fix OHCI clock gating for H3/H5 In-Reply-To: <20180507073351.30582-1-jagan@amarulasolutions.com> References: <20180507073351.30582-1-jagan@amarulasolutions.com> Message-ID: <20180507073351.30582-9-jagan@amarulasolutions.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Chen-Yu Tsai Clock gating bits on H43/H5 were wrong, fix them. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jagan Teki --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index c5dea45985..6fa6cf40ee 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -351,13 +351,10 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) #ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) #else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) -- 2.14.3