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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 6/7] drm/i915/execlists: Direct submission from irq handler
Date: Mon,  7 May 2018 10:25:26 +0100	[thread overview]
Message-ID: <20180507092527.7359-6-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20180507092527.7359-1-chris@chris-wilson.co.uk>

Continuing the themem of bypassing ksoftirqd latency, also first try to
directly submit from the CS interrupt handler to clear the ELSP and
queue the next.

In the past, we have been hesitant to do this as the context switch
processing has been quite heavy, requiring forcewaked mmio. However, as
we now can read the GPU state from the cacheable HWSP, it is relatively
cheap!

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         | 10 ++++------
 drivers/gpu/drm/i915/intel_ringbuffer.h | 11 +++++++++++
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f9bc3aaa90d0..ce5efb0cbb88 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1465,11 +1465,9 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	bool tasklet = false;
 
-	if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
-		if (READ_ONCE(engine->execlists.active))
-			tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
-						    &engine->irq_posted);
-	}
+	if (iir & GT_CONTEXT_SWITCH_INTERRUPT && READ_ONCE(execlists->active))
+		tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
+					    &engine->irq_posted);
 
 	if (iir & GT_RENDER_USER_INTERRUPT) {
 		notify_ring(engine);
@@ -1477,7 +1475,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
 	}
 
 	if (tasklet)
-		tasklet_hi_schedule(&execlists->tasklet);
+		execlists_tasklet(execlists);
 }
 
 static void gen8_gt_irq_ack(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f5545391d76a..670b0837e2f6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -717,6 +717,17 @@ execlists_port_complete(struct intel_engine_execlists * const execlists,
 	return port;
 }
 
+static inline void
+execlists_tasklet(struct intel_engine_execlists * const execlists)
+{
+	if (tasklet_trylock(&execlists->tasklet)) {
+		execlists->tasklet.func(execlists->tasklet.data);
+		tasklet_unlock(&execlists->tasklet);
+	} else {
+		tasklet_hi_schedule(&execlists->tasklet);
+	}
+}
+
 static inline unsigned int
 intel_engine_flag(const struct intel_engine_cs *engine)
 {
-- 
2.17.0

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  parent reply	other threads:[~2018-05-07  9:26 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-07  9:25 [PATCH 1/7] drm/i915: Flush submission tasklet after bumping priority Chris Wilson
2018-05-07  9:25 ` [PATCH 2/7] drm/i915: Combine set-wedged protection and tasklet kicking Chris Wilson
2018-05-07 12:09   ` Mika Kuoppala
2018-05-07 12:16     ` Chris Wilson
2018-05-07  9:25 ` [PATCH 3/7] drm/i915/execlists: Make submission tasklet hardirq safe Chris Wilson
2018-05-07  9:25 ` [PATCH 4/7] drm/i915/guc: " Chris Wilson
2018-05-07  9:25 ` [PATCH 5/7] drm/i915/execlists: Direct submit onto idle engines Chris Wilson
2018-05-07  9:25 ` Chris Wilson [this message]
2018-05-07  9:25 ` [PATCH 7/7] drm/i915: Speed up idle detection by kicking the tasklets Chris Wilson
2018-05-07  9:35   ` [PATCH v3] " Chris Wilson
2018-05-07 14:08     ` kbuild test robot
2018-05-07  9:33 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority Patchwork
2018-05-07  9:35 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-07  9:52 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-05-07  9:57 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Flush submission tasklet after bumping priority (rev2) Patchwork
2018-05-07  9:59 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-07 10:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-05-07 11:15 ` [PATCH 1/7] drm/i915: Flush submission tasklet after bumping priority Mika Kuoppala
2018-05-07 11:19   ` Chris Wilson

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