From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eduardo Habkost Subject: Re: [PATCH v7 7/9] i386: Add support for CPUID_8000_001E for AMD Date: Tue, 8 May 2018 11:16:32 -0300 Message-ID: <20180508141632.GJ25013@localhost.localdomain> References: <1524760009-24710-1-git-send-email-babu.moger@amd.com> <1524760009-24710-8-git-send-email-babu.moger@amd.com> <20180507193944.GF13350@localhost.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "geoff@hostfission.com" , "kvm@vger.kernel.org" , "mst@redhat.com" , "kash@tripleback.net" , "mtosatti@redhat.com" , "qemu-devel@nongnu.org" , "marcel@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" To: "Moger, Babu" Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel2=m.gmane.org@nongnu.org Sender: "Qemu-devel" List-Id: kvm.vger.kernel.org On Mon, May 07, 2018 at 11:44:31PM +0000, Moger, Babu wrote: [...] > > > + > > > /* > > > * Encode cache info for CPUID[0x80000006].ECX and > > CPUID[0x80000006].EDX > > > * @l3 can be NULL. > > > @@ -4105,6 +4111,14 @@ void cpu_x86_cpuid(CPUX86State *env, > > uint32_t index, uint32_t count, > > > break; > > > } > > > break; > > > + case 0x8000001E: > > > + assert(cpu->core_id <= 255); > > > > Where's the code that ensures this assert() line can't be > > triggered by any command-line configuration? > > I did not understand this. Can you please elaborate. Thanks The user must not be able to trigger an assert(), so we need to ensure that core_id will never be larger than 255. Is there existing code that ensures that? > > > > > > + *eax = EXTENDED_APIC_ID((cs->nr_threads - 1), > > > + cpu->socket_id, cpu->core_id, cpu->thread_id); > > > + *ebx = (cs->nr_threads - 1) << 8 | cpu->core_id; > > > + *ecx = cpu->socket_id; > > > + *edx = 0; > > > + break; > > > case 0xC0000000: > > > *eax = env->cpuid_xlevel2; > > > *ebx = 0; > > > -- > > > 2.7.4 > > > > > > > > > > -- > > Eduardo -- Eduardo From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG3Q5-0007ok-63 for qemu-devel@nongnu.org; Tue, 08 May 2018 10:16:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fG3Q1-0001OH-92 for qemu-devel@nongnu.org; Tue, 08 May 2018 10:16:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44488) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fG3Q1-0001OA-3M for qemu-devel@nongnu.org; Tue, 08 May 2018 10:16:41 -0400 Date: Tue, 8 May 2018 11:16:32 -0300 From: Eduardo Habkost Message-ID: <20180508141632.GJ25013@localhost.localdomain> References: <1524760009-24710-1-git-send-email-babu.moger@amd.com> <1524760009-24710-8-git-send-email-babu.moger@amd.com> <20180507193944.GF13350@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v7 7/9] i386: Add support for CPUID_8000_001E for AMD List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Moger, Babu" Cc: "mst@redhat.com" , "marcel@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "mtosatti@redhat.com" , "geoff@hostfission.com" , "kash@tripleback.net" , "qemu-devel@nongnu.org" , "kvm@vger.kernel.org" On Mon, May 07, 2018 at 11:44:31PM +0000, Moger, Babu wrote: [...] > > > + > > > /* > > > * Encode cache info for CPUID[0x80000006].ECX and > > CPUID[0x80000006].EDX > > > * @l3 can be NULL. > > > @@ -4105,6 +4111,14 @@ void cpu_x86_cpuid(CPUX86State *env, > > uint32_t index, uint32_t count, > > > break; > > > } > > > break; > > > + case 0x8000001E: > > > + assert(cpu->core_id <= 255); > > > > Where's the code that ensures this assert() line can't be > > triggered by any command-line configuration? > > I did not understand this. Can you please elaborate. Thanks The user must not be able to trigger an assert(), so we need to ensure that core_id will never be larger than 255. Is there existing code that ensures that? > > > > > > + *eax = EXTENDED_APIC_ID((cs->nr_threads - 1), > > > + cpu->socket_id, cpu->core_id, cpu->thread_id); > > > + *ebx = (cs->nr_threads - 1) << 8 | cpu->core_id; > > > + *ecx = cpu->socket_id; > > > + *edx = 0; > > > + break; > > > case 0xC0000000: > > > *eax = env->cpuid_xlevel2; > > > *ebx = 0; > > > -- > > > 2.7.4 > > > > > > > > > > -- > > Eduardo -- Eduardo