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From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3 0/6] drm/i915: per context slice/subslice powergating
Date: Tue,  8 May 2018 19:03:41 +0100	[thread overview]
Message-ID: <20180508180347.32080-1-lionel.g.landwerlin@intel.com> (raw)

Hi all,

Another update, trying to minimize the number of reprogramming issued
due to powergating configuration changes. This is achieved by tracking
the last submitted powergating configuration in the engine submission
mechanism and reprogramming only on configuration changes.

Another improvement that could be applied to limit the number of
changes in the powergating configuration could be :

   - to align all contexts to a given configuration (implictly discard
     the userspace requests).

   - within the submission mechanism, have a round robin scheduling
     that switches between buckets of contexts of different
     powergating configuration

This series doesn't include such mechanisms, it's probably best for me
to leave that to people who are more experienced.

Cheers,

Chris Wilson (3):
  drm/i915: Program RPCS for Broadwell
  drm/i915: Record the sseu configuration per-context & engine
  drm/i915: Expose RPCS (SSEU) configuration to userspace

Lionel Landwerlin (3):
  drm/i915/perf: simplify configure all context function
  drm/i915: reprogram NOA muxes on context switch when using perf
  drm/i915: count powergating transitions per engine

 drivers/gpu/drm/i915/i915_drv.h           |   6 +
 drivers/gpu/drm/i915/i915_gem.h           |  13 ++
 drivers/gpu/drm/i915/i915_gem_context.c   | 117 ++++++++++++++++-
 drivers/gpu/drm/i915/i915_gem_context.h   |   3 +
 drivers/gpu/drm/i915/i915_perf.c          | 119 ++++++++++++++++--
 drivers/gpu/drm/i915/i915_request.h       |   6 +
 drivers/gpu/drm/i915/intel_engine_cs.c    |   2 +
 drivers/gpu/drm/i915/intel_gpu_commands.h |   1 +
 drivers/gpu/drm/i915/intel_lrc.c          | 146 +++++++++++++++++++---
 drivers/gpu/drm/i915/intel_lrc.h          |   4 +
 drivers/gpu/drm/i915/intel_ringbuffer.c   |   3 +
 drivers/gpu/drm/i915/intel_ringbuffer.h   |   3 +
 include/uapi/drm/i915_drm.h               |  38 ++++++
 13 files changed, 433 insertions(+), 28 deletions(-)

--
2.17.0
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             reply	other threads:[~2018-05-08 18:03 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-08 18:03 Lionel Landwerlin [this message]
2018-05-08 18:03 ` [PATCH v3 1/6] drm/i915: Program RPCS for Broadwell Lionel Landwerlin
2018-05-08 18:03 ` [PATCH v3 2/6] drm/i915: Record the sseu configuration per-context & engine Lionel Landwerlin
2018-05-08 18:03 ` [PATCH v3 3/6] drm/i915/perf: simplify configure all context function Lionel Landwerlin
2018-05-08 18:03 ` [PATCH v3 4/6] drm/i915: reprogram NOA muxes on context switch when using perf Lionel Landwerlin
2018-05-09  8:59   ` Chris Wilson
2018-05-09  9:05     ` Chris Wilson
2018-05-09  9:23       ` Lionel Landwerlin
2018-05-09  9:12     ` Lionel Landwerlin
2018-05-09 15:31     ` Lionel Landwerlin
2018-05-08 18:03 ` [PATCH v3 5/6] drm/i915: count powergating transitions per engine Lionel Landwerlin
2018-05-08 18:03 ` [PATCH v3 6/6] drm/i915: Expose RPCS (SSEU) configuration to userspace Lionel Landwerlin
2018-05-08 18:33 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: per context slice/subslice powergating (rev2) Patchwork
2018-05-08 18:35 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-08 18:51 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-08 22:34 ` ✗ Fi.CI.IGT: failure " Patchwork

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