From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934536AbeEJIJx (ORCPT ); Thu, 10 May 2018 04:09:53 -0400 Received: from mx2.suse.de ([195.135.220.15]:51761 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756798AbeEJIHI (ORCPT ); Thu, 10 May 2018 04:07:08 -0400 From: Jiri Slaby To: mingo@redhat.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Jiri Slaby , Thomas Gleixner , "H. Peter Anvin" , x86@kernel.org, Boris Ostrovsky , Juergen Gross , xen-devel@lists.xenproject.org Subject: [PATCH -resend 22/27] x86_64: assembly, change all ENTRY+END to SYM_CODE_* Date: Thu, 10 May 2018 10:06:39 +0200 Message-Id: <20180510080644.19752-23-jslaby@suse.cz> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20180510080644.19752-1-jslaby@suse.cz> References: <20180510080644.19752-1-jslaby@suse.cz> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Here, we change all code which is not marked as functions. In other words, this code has been using END, not ENDPROC. So switch all of this to appropriate new markings SYM_CODE_START and SYM_CODE_END. Signed-off-by: Jiri Slaby Reviewed-by: Boris Ostrovsky [xen bits] Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: Boris Ostrovsky Cc: Juergen Gross Cc: xen-devel@lists.xenproject.org --- arch/x86/entry/entry_64.S | 56 ++++++++++++++++++++-------------------- arch/x86/entry/entry_64_compat.S | 8 +++--- arch/x86/kernel/ftrace_64.S | 4 +-- arch/x86/xen/xen-asm_64.S | 8 +++--- arch/x86/xen/xen-head.S | 8 +++--- 5 files changed, 42 insertions(+), 42 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index c6841c038170..1b0631971dde 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -46,11 +46,11 @@ .section .entry.text, "ax" #ifdef CONFIG_PARAVIRT -ENTRY(native_usergs_sysret64) +SYM_CODE_START(native_usergs_sysret64) UNWIND_HINT_EMPTY swapgs sysretq -END(native_usergs_sysret64) +SYM_CODE_END(native_usergs_sysret64) #endif /* CONFIG_PARAVIRT */ .macro TRACE_IRQS_FLAGS flags:req @@ -163,7 +163,7 @@ END(native_usergs_sysret64) #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA -ENTRY(entry_SYSCALL_64_trampoline) +SYM_CODE_START(entry_SYSCALL_64_trampoline) UNWIND_HINT_EMPTY swapgs @@ -193,17 +193,17 @@ ENTRY(entry_SYSCALL_64_trampoline) pushq %rdi movq $entry_SYSCALL_64_stage2, %rdi JMP_NOSPEC %rdi -END(entry_SYSCALL_64_trampoline) +SYM_CODE_END(entry_SYSCALL_64_trampoline) .popsection -ENTRY(entry_SYSCALL_64_stage2) +SYM_CODE_START(entry_SYSCALL_64_stage2) UNWIND_HINT_EMPTY popq %rdi jmp entry_SYSCALL_64_after_hwframe -END(entry_SYSCALL_64_stage2) +SYM_CODE_END(entry_SYSCALL_64_stage2) -ENTRY(entry_SYSCALL_64) +SYM_CODE_START(entry_SYSCALL_64) UNWIND_HINT_EMPTY /* * Interrupts are off on entry. @@ -336,13 +336,13 @@ syscall_return_via_sysret: popq %rdi popq %rsp USERGS_SYSRET64 -END(entry_SYSCALL_64) +SYM_CODE_END(entry_SYSCALL_64) /* * %rdi: prev task * %rsi: next task */ -ENTRY(__switch_to_asm) +SYM_CODE_START(__switch_to_asm) UNWIND_HINT_FUNC /* * Save callee-saved registers @@ -384,7 +384,7 @@ ENTRY(__switch_to_asm) popq %rbp jmp __switch_to -END(__switch_to_asm) +SYM_CODE_END(__switch_to_asm) /* * A newly forked process directly context switches into this address. @@ -393,7 +393,7 @@ END(__switch_to_asm) * rbx: kernel thread func (NULL for user thread) * r12: kernel thread arg */ -ENTRY(ret_from_fork) +SYM_CODE_START(ret_from_fork) UNWIND_HINT_EMPTY movq %rax, %rdi call schedule_tail /* rdi: 'prev' task parameter */ @@ -419,14 +419,14 @@ ENTRY(ret_from_fork) */ movq $0, RAX(%rsp) jmp 2b -END(ret_from_fork) +SYM_CODE_END(ret_from_fork) /* * Build the entry stubs with some assembler magic. * We pack 1 stub into every 8-byte block. */ .align 8 -ENTRY(irq_entries_start) +SYM_CODE_START(irq_entries_start) vector=FIRST_EXTERNAL_VECTOR .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) UNWIND_HINT_IRET_REGS @@ -435,7 +435,7 @@ ENTRY(irq_entries_start) .align 8 vector=vector+1 .endr -END(irq_entries_start) +SYM_CODE_END(irq_entries_start) .macro DEBUG_ENTRY_ASSERT_IRQS_OFF #ifdef CONFIG_DEBUG_ENTRY @@ -561,7 +561,7 @@ END(irq_entries_start) * | return address | * +----------------------------------------------------+ */ -ENTRY(interrupt_entry) +SYM_CODE_START(interrupt_entry) UNWIND_HINT_FUNC ASM_CLAC cld @@ -627,7 +627,7 @@ ENTRY(interrupt_entry) TRACE_IRQS_OFF ret -END(interrupt_entry) +SYM_CODE_END(interrupt_entry) /* Interrupt entry/exit. */ @@ -832,7 +832,7 @@ SYM_CODE_END(common_interrupt) * APIC interrupts. */ .macro apicinterrupt3 num sym do_sym -ENTRY(\sym) +SYM_CODE_START(\sym) UNWIND_HINT_IRET_REGS pushq $~(\num) .Lcommon_\sym: @@ -840,7 +840,7 @@ ENTRY(\sym) UNWIND_HINT_REGS indirect=1 call \do_sym /* rdi points to pt_regs */ jmp ret_from_intr -END(\sym) +SYM_CODE_END(\sym) .endm /* Make sure APIC interrupt handlers end up in the irqentry section: */ @@ -902,7 +902,7 @@ apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 -ENTRY(\sym) +SYM_CODE_START(\sym) UNWIND_HINT_IRET_REGS offset=\has_error_code*8 /* Sanity check */ @@ -985,7 +985,7 @@ ENTRY(\sym) jmp error_exit /* %ebx: no swapgs flag */ .endif -END(\sym) +SYM_CODE_END(\sym) .endm idtentry divide_error do_divide_error has_error_code=0 @@ -1102,7 +1102,7 @@ SYM_CODE_END(xen_do_hypervisor_callback) * We distinguish between categories by comparing each saved segment register * with its current contents: any discrepancy means we in category 1. */ -ENTRY(xen_failsafe_callback) +SYM_CODE_START(xen_failsafe_callback) UNWIND_HINT_EMPTY movl %ds, %ecx cmpw %cx, 0x10(%rsp) @@ -1132,7 +1132,7 @@ ENTRY(xen_failsafe_callback) PUSH_AND_CLEAR_REGS ENCODE_FRAME_POINTER jmp error_exit -END(xen_failsafe_callback) +SYM_CODE_END(xen_failsafe_callback) apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ xen_hvm_callback_vector xen_evtchn_do_upcall @@ -1340,7 +1340,7 @@ SYM_CODE_END(error_exit) * %r14: Used to save/restore the CR3 of the interrupted context * when PAGE_TABLE_ISOLATION is in use. Do not clobber. */ -ENTRY(nmi) +SYM_CODE_START(nmi) UNWIND_HINT_IRET_REGS /* @@ -1673,15 +1673,15 @@ nmi_restore: * about espfix64 on the way back to kernel mode. */ iretq -END(nmi) +SYM_CODE_END(nmi) -ENTRY(ignore_sysret) +SYM_CODE_START(ignore_sysret) UNWIND_HINT_EMPTY mov $-ENOSYS, %eax sysret -END(ignore_sysret) +SYM_CODE_END(ignore_sysret) -ENTRY(rewind_stack_do_exit) +SYM_CODE_START(rewind_stack_do_exit) UNWIND_HINT_FUNC /* Prevent any naive code from trying to unwind to our caller. */ xorl %ebp, %ebp @@ -1691,4 +1691,4 @@ ENTRY(rewind_stack_do_exit) UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE call do_exit -END(rewind_stack_do_exit) +SYM_CODE_END(rewind_stack_do_exit) diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index 076659472d40..b4a2ee901899 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -196,7 +196,7 @@ ENDPROC(entry_SYSENTER_compat) * esp user stack * 0(%esp) arg6 */ -ENTRY(entry_SYSCALL_compat) +SYM_CODE_START(entry_SYSCALL_compat) /* Interrupts are off on entry. */ swapgs @@ -311,7 +311,7 @@ sysret32_from_system_call: xorl %r10d, %r10d swapgs sysretl -END(entry_SYSCALL_compat) +SYM_CODE_END(entry_SYSCALL_compat) /* * 32-bit legacy system call entry. @@ -339,7 +339,7 @@ END(entry_SYSCALL_compat) * edi arg5 * ebp arg6 */ -ENTRY(entry_INT80_compat) +SYM_CODE_START(entry_INT80_compat) /* * Interrupts are off on entry. */ @@ -414,4 +414,4 @@ ENTRY(entry_INT80_compat) /* Go back to user mode. */ TRACE_IRQS_ON jmp swapgs_restore_regs_and_return_to_usermode -END(entry_INT80_compat) +SYM_CODE_END(entry_INT80_compat) diff --git a/arch/x86/kernel/ftrace_64.S b/arch/x86/kernel/ftrace_64.S index b50fbb405763..141341eaa267 100644 --- a/arch/x86/kernel/ftrace_64.S +++ b/arch/x86/kernel/ftrace_64.S @@ -319,7 +319,7 @@ ENTRY(ftrace_graph_caller) retq ENDPROC(ftrace_graph_caller) -ENTRY(return_to_handler) +SYM_CODE_START(return_to_handler) UNWIND_HINT_EMPTY subq $24, %rsp @@ -335,5 +335,5 @@ ENTRY(return_to_handler) movq (%rsp), %rax addq $24, %rsp JMP_NOSPEC %rdi -END(return_to_handler) +SYM_CODE_END(return_to_handler) #endif diff --git a/arch/x86/xen/xen-asm_64.S b/arch/x86/xen/xen-asm_64.S index a69a171f7cea..5a3f5c18cd0c 100644 --- a/arch/x86/xen/xen-asm_64.S +++ b/arch/x86/xen/xen-asm_64.S @@ -19,11 +19,11 @@ #include .macro xen_pv_trap name -ENTRY(xen_\name) +SYM_CODE_START(xen_\name) pop %rcx pop %r11 jmp \name -END(xen_\name) +SYM_CODE_END(xen_\name) .endm xen_pv_trap divide_error @@ -56,7 +56,7 @@ xen_pv_trap entry_INT80_compat xen_pv_trap hypervisor_callback __INIT -ENTRY(xen_early_idt_handler_array) +SYM_CODE_START(xen_early_idt_handler_array) i = 0 .rept NUM_EXCEPTION_VECTORS pop %rcx @@ -65,7 +65,7 @@ ENTRY(xen_early_idt_handler_array) i = i + 1 .fill xen_early_idt_handler_array + i*XEN_EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc .endr -END(xen_early_idt_handler_array) +SYM_CODE_END(xen_early_idt_handler_array) __FINIT hypercall_iret = hypercall_page + __HYPERVISOR_iret * 32 diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S index 5077ead5e59c..32606eeec053 100644 --- a/arch/x86/xen/xen-head.S +++ b/arch/x86/xen/xen-head.S @@ -22,7 +22,7 @@ #ifdef CONFIG_XEN_PV __INIT -ENTRY(startup_xen) +SYM_CODE_START(startup_xen) UNWIND_HINT_EMPTY cld @@ -52,13 +52,13 @@ ENTRY(startup_xen) #endif jmp xen_start_kernel -END(startup_xen) +SYM_CODE_END(startup_xen) __FINIT #endif .pushsection .text .balign PAGE_SIZE -ENTRY(hypercall_page) +SYM_CODE_START(hypercall_page) .rept (PAGE_SIZE / 32) UNWIND_HINT_EMPTY .skip 32 @@ -69,7 +69,7 @@ ENTRY(hypercall_page) .type xen_hypercall_##n, @function; .size xen_hypercall_##n, 32 #include #undef HYPERCALL -END(hypercall_page) +SYM_CODE_END(hypercall_page) .popsection ELFNOTE(Xen, XEN_ELFNOTE_GUEST_OS, .asciz "linux") -- 2.16.3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jiri Slaby Subject: [PATCH -resend 22/27] x86_64: assembly, change all ENTRY+END to SYM_CODE_* Date: Thu, 10 May 2018 10:06:39 +0200 Message-ID: <20180510080644.19752-23-jslaby@suse.cz> References: <20180510080644.19752-1-jslaby@suse.cz> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180510080644.19752-1-jslaby@suse.cz> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: mingo@redhat.com Cc: linux-arch@vger.kernel.org, Juergen Gross , x86@kernel.org, linux-kernel@vger.kernel.org, "H. Peter Anvin" , xen-devel@lists.xenproject.org, Thomas Gleixner , Jiri Slaby , Boris Ostrovsky List-Id: linux-arch.vger.kernel.org SGVyZSwgd2UgY2hhbmdlIGFsbCBjb2RlIHdoaWNoIGlzIG5vdCBtYXJrZWQgYXMgZnVuY3Rpb25z LiBJbiBvdGhlcgp3b3JkcywgdGhpcyBjb2RlIGhhcyBiZWVuIHVzaW5nIEVORCwgbm90IEVORFBS T0MuIFNvIHN3aXRjaCBhbGwgb2YgdGhpcwp0byBhcHByb3ByaWF0ZSBuZXcgbWFya2luZ3MgU1lN X0NPREVfU1RBUlQgYW5kIFNZTV9DT0RFX0VORC4KClNpZ25lZC1vZmYtYnk6IEppcmkgU2xhYnkg PGpzbGFieUBzdXNlLmN6PgpSZXZpZXdlZC1ieTogQm9yaXMgT3N0cm92c2t5IDxib3Jpcy5vc3Ry b3Zza3lAb3JhY2xlLmNvbT4gW3hlbiBiaXRzXQpDYzogVGhvbWFzIEdsZWl4bmVyIDx0Z2x4QGxp bnV0cm9uaXguZGU+CkNjOiBJbmdvIE1vbG5hciA8bWluZ29AcmVkaGF0LmNvbT4KQ2M6ICJILiBQ ZXRlciBBbnZpbiIgPGhwYUB6eXRvci5jb20+CkNjOiB4ODZAa2VybmVsLm9yZwpDYzogQm9yaXMg T3N0cm92c2t5IDxib3Jpcy5vc3Ryb3Zza3lAb3JhY2xlLmNvbT4KQ2M6IEp1ZXJnZW4gR3Jvc3Mg PGpncm9zc0BzdXNlLmNvbT4KQ2M6IHhlbi1kZXZlbEBsaXN0cy54ZW5wcm9qZWN0Lm9yZwotLS0K IGFyY2gveDg2L2VudHJ5L2VudHJ5XzY0LlMgICAgICAgIHwgNTYgKysrKysrKysrKysrKysrKysr KystLS0tLS0tLS0tLS0tLS0tLS0tLQogYXJjaC94ODYvZW50cnkvZW50cnlfNjRfY29tcGF0LlMg fCAgOCArKystLS0KIGFyY2gveDg2L2tlcm5lbC9mdHJhY2VfNjQuUyAgICAgIHwgIDQgKy0tCiBh cmNoL3g4Ni94ZW4veGVuLWFzbV82NC5TICAgICAgICB8ICA4ICsrKy0tLQogYXJjaC94ODYveGVu L3hlbi1oZWFkLlMgICAgICAgICAgfCAgOCArKystLS0KIDUgZmlsZXMgY2hhbmdlZCwgNDIgaW5z ZXJ0aW9ucygrKSwgNDIgZGVsZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEvYXJjaC94ODYvZW50cnkv ZW50cnlfNjQuUyBiL2FyY2gveDg2L2VudHJ5L2VudHJ5XzY0LlMKaW5kZXggYzY4NDFjMDM4MTcw Li4xYjA2MzE5NzFkZGUgMTAwNjQ0Ci0tLSBhL2FyY2gveDg2L2VudHJ5L2VudHJ5XzY0LlMKKysr IGIvYXJjaC94ODYvZW50cnkvZW50cnlfNjQuUwpAQCAtNDYsMTEgKzQ2LDExIEBACiAuc2VjdGlv biAuZW50cnkudGV4dCwgImF4IgogCiAjaWZkZWYgQ09ORklHX1BBUkFWSVJUCi1FTlRSWShuYXRp dmVfdXNlcmdzX3N5c3JldDY0KQorU1lNX0NPREVfU1RBUlQobmF0aXZlX3VzZXJnc19zeXNyZXQ2 NCkKIAlVTldJTkRfSElOVF9FTVBUWQogCXN3YXBncwogCXN5c3JldHEKLUVORChuYXRpdmVfdXNl cmdzX3N5c3JldDY0KQorU1lNX0NPREVfRU5EKG5hdGl2ZV91c2VyZ3Nfc3lzcmV0NjQpCiAjZW5k aWYgLyogQ09ORklHX1BBUkFWSVJUICovCiAKIC5tYWNybyBUUkFDRV9JUlFTX0ZMQUdTIGZsYWdz OnJlcQpAQCAtMTYzLDcgKzE2Myw3IEBAIEVORChuYXRpdmVfdXNlcmdzX3N5c3JldDY0KQogI2Rl ZmluZSBSU1BfU0NSQVRDSAlDUFVfRU5UUllfQVJFQV9lbnRyeV9zdGFjayArIFwKIAkJCVNJWkVP Rl9lbnRyeV9zdGFjayAtIDggKyBDUFVfRU5UUllfQVJFQQogCi1FTlRSWShlbnRyeV9TWVNDQUxM XzY0X3RyYW1wb2xpbmUpCitTWU1fQ09ERV9TVEFSVChlbnRyeV9TWVNDQUxMXzY0X3RyYW1wb2xp bmUpCiAJVU5XSU5EX0hJTlRfRU1QVFkKIAlzd2FwZ3MKIApAQCAtMTkzLDE3ICsxOTMsMTcgQEAg RU5UUlkoZW50cnlfU1lTQ0FMTF82NF90cmFtcG9saW5lKQogCXB1c2hxCSVyZGkKIAltb3ZxCSRl bnRyeV9TWVNDQUxMXzY0X3N0YWdlMiwgJXJkaQogCUpNUF9OT1NQRUMgJXJkaQotRU5EKGVudHJ5 X1NZU0NBTExfNjRfdHJhbXBvbGluZSkKK1NZTV9DT0RFX0VORChlbnRyeV9TWVNDQUxMXzY0X3Ry YW1wb2xpbmUpCiAKIAkucG9wc2VjdGlvbgogCi1FTlRSWShlbnRyeV9TWVNDQUxMXzY0X3N0YWdl MikKK1NZTV9DT0RFX1NUQVJUKGVudHJ5X1NZU0NBTExfNjRfc3RhZ2UyKQogCVVOV0lORF9ISU5U X0VNUFRZCiAJcG9wcQklcmRpCiAJam1wCWVudHJ5X1NZU0NBTExfNjRfYWZ0ZXJfaHdmcmFtZQot RU5EKGVudHJ5X1NZU0NBTExfNjRfc3RhZ2UyKQorU1lNX0NPREVfRU5EKGVudHJ5X1NZU0NBTExf NjRfc3RhZ2UyKQogCi1FTlRSWShlbnRyeV9TWVNDQUxMXzY0KQorU1lNX0NPREVfU1RBUlQoZW50 cnlfU1lTQ0FMTF82NCkKIAlVTldJTkRfSElOVF9FTVBUWQogCS8qCiAJICogSW50ZXJydXB0cyBh cmUgb2ZmIG9uIGVudHJ5LgpAQCAtMzM2LDEzICszMzYsMTMgQEAgc3lzY2FsbF9yZXR1cm5fdmlh X3N5c3JldDoKIAlwb3BxCSVyZGkKIAlwb3BxCSVyc3AKIAlVU0VSR1NfU1lTUkVUNjQKLUVORChl bnRyeV9TWVNDQUxMXzY0KQorU1lNX0NPREVfRU5EKGVudHJ5X1NZU0NBTExfNjQpCiAKIC8qCiAg KiAlcmRpOiBwcmV2IHRhc2sKICAqICVyc2k6IG5leHQgdGFzawogICovCi1FTlRSWShfX3N3aXRj aF90b19hc20pCitTWU1fQ09ERV9TVEFSVChfX3N3aXRjaF90b19hc20pCiAJVU5XSU5EX0hJTlRf RlVOQwogCS8qCiAJICogU2F2ZSBjYWxsZWUtc2F2ZWQgcmVnaXN0ZXJzCkBAIC0zODQsNyArMzg0 LDcgQEAgRU5UUlkoX19zd2l0Y2hfdG9fYXNtKQogCXBvcHEJJXJicAogCiAJam1wCV9fc3dpdGNo X3RvCi1FTkQoX19zd2l0Y2hfdG9fYXNtKQorU1lNX0NPREVfRU5EKF9fc3dpdGNoX3RvX2FzbSkK IAogLyoKICAqIEEgbmV3bHkgZm9ya2VkIHByb2Nlc3MgZGlyZWN0bHkgY29udGV4dCBzd2l0Y2hl cyBpbnRvIHRoaXMgYWRkcmVzcy4KQEAgLTM5Myw3ICszOTMsNyBAQCBFTkQoX19zd2l0Y2hfdG9f YXNtKQogICogcmJ4OiBrZXJuZWwgdGhyZWFkIGZ1bmMgKE5VTEwgZm9yIHVzZXIgdGhyZWFkKQog ICogcjEyOiBrZXJuZWwgdGhyZWFkIGFyZwogICovCi1FTlRSWShyZXRfZnJvbV9mb3JrKQorU1lN X0NPREVfU1RBUlQocmV0X2Zyb21fZm9yaykKIAlVTldJTkRfSElOVF9FTVBUWQogCW1vdnEJJXJh eCwgJXJkaQogCWNhbGwJc2NoZWR1bGVfdGFpbAkJCS8qIHJkaTogJ3ByZXYnIHRhc2sgcGFyYW1l dGVyICovCkBAIC00MTksMTQgKzQxOSwxNCBAQCBFTlRSWShyZXRfZnJvbV9mb3JrKQogCSAqLwog CW1vdnEJJDAsIFJBWCglcnNwKQogCWptcAkyYgotRU5EKHJldF9mcm9tX2ZvcmspCitTWU1fQ09E RV9FTkQocmV0X2Zyb21fZm9yaykKIAogLyoKICAqIEJ1aWxkIHRoZSBlbnRyeSBzdHVicyB3aXRo IHNvbWUgYXNzZW1ibGVyIG1hZ2ljLgogICogV2UgcGFjayAxIHN0dWIgaW50byBldmVyeSA4LWJ5 dGUgYmxvY2suCiAgKi8KIAkuYWxpZ24gOAotRU5UUlkoaXJxX2VudHJpZXNfc3RhcnQpCitTWU1f Q09ERV9TVEFSVChpcnFfZW50cmllc19zdGFydCkKICAgICB2ZWN0b3I9RklSU1RfRVhURVJOQUxf VkVDVE9SCiAgICAgLnJlcHQgKEZJUlNUX1NZU1RFTV9WRUNUT1IgLSBGSVJTVF9FWFRFUk5BTF9W RUNUT1IpCiAJVU5XSU5EX0hJTlRfSVJFVF9SRUdTCkBAIC00MzUsNyArNDM1LDcgQEAgRU5UUlko aXJxX2VudHJpZXNfc3RhcnQpCiAJLmFsaWduCTgKIAl2ZWN0b3I9dmVjdG9yKzEKICAgICAuZW5k cgotRU5EKGlycV9lbnRyaWVzX3N0YXJ0KQorU1lNX0NPREVfRU5EKGlycV9lbnRyaWVzX3N0YXJ0 KQogCiAubWFjcm8gREVCVUdfRU5UUllfQVNTRVJUX0lSUVNfT0ZGCiAjaWZkZWYgQ09ORklHX0RF QlVHX0VOVFJZCkBAIC01NjEsNyArNTYxLDcgQEAgRU5EKGlycV9lbnRyaWVzX3N0YXJ0KQogICog fCByZXR1cm4gYWRkcmVzcwkJCQkJfAogICogKy0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0rCiAgKi8KLUVOVFJZKGludGVycnVwdF9lbnRyeSkKK1NZ TV9DT0RFX1NUQVJUKGludGVycnVwdF9lbnRyeSkKIAlVTldJTkRfSElOVF9GVU5DCiAJQVNNX0NM QUMKIAljbGQKQEAgLTYyNyw3ICs2MjcsNyBAQCBFTlRSWShpbnRlcnJ1cHRfZW50cnkpCiAJVFJB Q0VfSVJRU19PRkYKIAogCXJldAotRU5EKGludGVycnVwdF9lbnRyeSkKK1NZTV9DT0RFX0VORChp bnRlcnJ1cHRfZW50cnkpCiAKIAogLyogSW50ZXJydXB0IGVudHJ5L2V4aXQuICovCkBAIC04MzIs NyArODMyLDcgQEAgU1lNX0NPREVfRU5EKGNvbW1vbl9pbnRlcnJ1cHQpCiAgKiBBUElDIGludGVy cnVwdHMuCiAgKi8KIC5tYWNybyBhcGljaW50ZXJydXB0MyBudW0gc3ltIGRvX3N5bQotRU5UUlko XHN5bSkKK1NZTV9DT0RFX1NUQVJUKFxzeW0pCiAJVU5XSU5EX0hJTlRfSVJFVF9SRUdTCiAJcHVz aHEJJH4oXG51bSkKIC5MY29tbW9uX1xzeW06CkBAIC04NDAsNyArODQwLDcgQEAgRU5UUlkoXHN5 bSkKIAlVTldJTkRfSElOVF9SRUdTIGluZGlyZWN0PTEKIAljYWxsCVxkb19zeW0JLyogcmRpIHBv aW50cyB0byBwdF9yZWdzICovCiAJam1wCXJldF9mcm9tX2ludHIKLUVORChcc3ltKQorU1lNX0NP REVfRU5EKFxzeW0pCiAuZW5kbQogCiAvKiBNYWtlIHN1cmUgQVBJQyBpbnRlcnJ1cHQgaGFuZGxl cnMgZW5kIHVwIGluIHRoZSBpcnFlbnRyeSBzZWN0aW9uOiAqLwpAQCAtOTAyLDcgKzkwMiw3IEBA IGFwaWNpbnRlcnJ1cHQgSVJRX1dPUktfVkVDVE9SCQkJaXJxX3dvcmtfaW50ZXJydXB0CQlzbXBf aXJxX3dvcmtfaW50ZXJydXB0CiAjZGVmaW5lIENQVV9UU1NfSVNUKHgpIFBFUl9DUFVfVkFSKGNw dV90c3NfcncpICsgKFRTU19pc3QgKyAoKHgpIC0gMSkgKiA4KQogCiAubWFjcm8gaWR0ZW50cnkg c3ltIGRvX3N5bSBoYXNfZXJyb3JfY29kZTpyZXEgcGFyYW5vaWQ9MCBzaGlmdF9pc3Q9LTEKLUVO VFJZKFxzeW0pCitTWU1fQ09ERV9TVEFSVChcc3ltKQogCVVOV0lORF9ISU5UX0lSRVRfUkVHUyBv ZmZzZXQ9XGhhc19lcnJvcl9jb2RlKjgKIAogCS8qIFNhbml0eSBjaGVjayAqLwpAQCAtOTg1LDcg Kzk4NSw3IEBAIEVOVFJZKFxzeW0pCiAKIAlqbXAJZXJyb3JfZXhpdAkJCS8qICVlYng6IG5vIHN3 YXBncyBmbGFnICovCiAJLmVuZGlmCi1FTkQoXHN5bSkKK1NZTV9DT0RFX0VORChcc3ltKQogLmVu ZG0KIAogaWR0ZW50cnkgZGl2aWRlX2Vycm9yCQkJZG9fZGl2aWRlX2Vycm9yCQkJaGFzX2Vycm9y X2NvZGU9MApAQCAtMTEwMiw3ICsxMTAyLDcgQEAgU1lNX0NPREVfRU5EKHhlbl9kb19oeXBlcnZp c29yX2NhbGxiYWNrKQogICogV2UgZGlzdGluZ3Vpc2ggYmV0d2VlbiBjYXRlZ29yaWVzIGJ5IGNv bXBhcmluZyBlYWNoIHNhdmVkIHNlZ21lbnQgcmVnaXN0ZXIKICAqIHdpdGggaXRzIGN1cnJlbnQg Y29udGVudHM6IGFueSBkaXNjcmVwYW5jeSBtZWFucyB3ZSBpbiBjYXRlZ29yeSAxLgogICovCi1F TlRSWSh4ZW5fZmFpbHNhZmVfY2FsbGJhY2spCitTWU1fQ09ERV9TVEFSVCh4ZW5fZmFpbHNhZmVf Y2FsbGJhY2spCiAJVU5XSU5EX0hJTlRfRU1QVFkKIAltb3ZsCSVkcywgJWVjeAogCWNtcHcJJWN4 LCAweDEwKCVyc3ApCkBAIC0xMTMyLDcgKzExMzIsNyBAQCBFTlRSWSh4ZW5fZmFpbHNhZmVfY2Fs bGJhY2spCiAJUFVTSF9BTkRfQ0xFQVJfUkVHUwogCUVOQ09ERV9GUkFNRV9QT0lOVEVSCiAJam1w CWVycm9yX2V4aXQKLUVORCh4ZW5fZmFpbHNhZmVfY2FsbGJhY2spCitTWU1fQ09ERV9FTkQoeGVu X2ZhaWxzYWZlX2NhbGxiYWNrKQogCiBhcGljaW50ZXJydXB0MyBIWVBFUlZJU09SX0NBTExCQUNL X1ZFQ1RPUiBcCiAJeGVuX2h2bV9jYWxsYmFja192ZWN0b3IgeGVuX2V2dGNobl9kb191cGNhbGwK QEAgLTEzNDAsNyArMTM0MCw3IEBAIFNZTV9DT0RFX0VORChlcnJvcl9leGl0KQogICoJJXIxNDog VXNlZCB0byBzYXZlL3Jlc3RvcmUgdGhlIENSMyBvZiB0aGUgaW50ZXJydXB0ZWQgY29udGV4dAog ICoJICAgICAgd2hlbiBQQUdFX1RBQkxFX0lTT0xBVElPTiBpcyBpbiB1c2UuICBEbyBub3QgY2xv YmJlci4KICAqLwotRU5UUlkobm1pKQorU1lNX0NPREVfU1RBUlQobm1pKQogCVVOV0lORF9ISU5U X0lSRVRfUkVHUwogCiAJLyoKQEAgLTE2NzMsMTUgKzE2NzMsMTUgQEAgbm1pX3Jlc3RvcmU6CiAJ ICogYWJvdXQgZXNwZml4NjQgb24gdGhlIHdheSBiYWNrIHRvIGtlcm5lbCBtb2RlLgogCSAqLwog CWlyZXRxCi1FTkQobm1pKQorU1lNX0NPREVfRU5EKG5taSkKIAotRU5UUlkoaWdub3JlX3N5c3Jl dCkKK1NZTV9DT0RFX1NUQVJUKGlnbm9yZV9zeXNyZXQpCiAJVU5XSU5EX0hJTlRfRU1QVFkKIAlt b3YJJC1FTk9TWVMsICVlYXgKIAlzeXNyZXQKLUVORChpZ25vcmVfc3lzcmV0KQorU1lNX0NPREVf RU5EKGlnbm9yZV9zeXNyZXQpCiAKLUVOVFJZKHJld2luZF9zdGFja19kb19leGl0KQorU1lNX0NP REVfU1RBUlQocmV3aW5kX3N0YWNrX2RvX2V4aXQpCiAJVU5XSU5EX0hJTlRfRlVOQwogCS8qIFBy ZXZlbnQgYW55IG5haXZlIGNvZGUgZnJvbSB0cnlpbmcgdG8gdW53aW5kIHRvIG91ciBjYWxsZXIu ICovCiAJeG9ybAklZWJwLCAlZWJwCkBAIC0xNjkxLDQgKzE2OTEsNCBAQCBFTlRSWShyZXdpbmRf c3RhY2tfZG9fZXhpdCkKIAlVTldJTkRfSElOVF9GVU5DIHNwX29mZnNldD1QVFJFR1NfU0laRQog CiAJY2FsbAlkb19leGl0Ci1FTkQocmV3aW5kX3N0YWNrX2RvX2V4aXQpCitTWU1fQ09ERV9FTkQo cmV3aW5kX3N0YWNrX2RvX2V4aXQpCmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9lbnRyeS9lbnRyeV82 NF9jb21wYXQuUyBiL2FyY2gveDg2L2VudHJ5L2VudHJ5XzY0X2NvbXBhdC5TCmluZGV4IDA3NjY1 OTQ3MmQ0MC4uYjRhMmVlOTAxODk5IDEwMDY0NAotLS0gYS9hcmNoL3g4Ni9lbnRyeS9lbnRyeV82 NF9jb21wYXQuUworKysgYi9hcmNoL3g4Ni9lbnRyeS9lbnRyeV82NF9jb21wYXQuUwpAQCAtMTk2 LDcgKzE5Niw3IEBAIEVORFBST0MoZW50cnlfU1lTRU5URVJfY29tcGF0KQogICogZXNwICB1c2Vy IHN0YWNrCiAgKiAwKCVlc3ApIGFyZzYKICAqLwotRU5UUlkoZW50cnlfU1lTQ0FMTF9jb21wYXQp CitTWU1fQ09ERV9TVEFSVChlbnRyeV9TWVNDQUxMX2NvbXBhdCkKIAkvKiBJbnRlcnJ1cHRzIGFy ZSBvZmYgb24gZW50cnkuICovCiAJc3dhcGdzCiAKQEAgLTMxMSw3ICszMTEsNyBAQCBzeXNyZXQz Ml9mcm9tX3N5c3RlbV9jYWxsOgogCXhvcmwJJXIxMGQsICVyMTBkCiAJc3dhcGdzCiAJc3lzcmV0 bAotRU5EKGVudHJ5X1NZU0NBTExfY29tcGF0KQorU1lNX0NPREVfRU5EKGVudHJ5X1NZU0NBTExf Y29tcGF0KQogCiAvKgogICogMzItYml0IGxlZ2FjeSBzeXN0ZW0gY2FsbCBlbnRyeS4KQEAgLTMz OSw3ICszMzksNyBAQCBFTkQoZW50cnlfU1lTQ0FMTF9jb21wYXQpCiAgKiBlZGkgIGFyZzUKICAq IGVicCAgYXJnNgogICovCi1FTlRSWShlbnRyeV9JTlQ4MF9jb21wYXQpCitTWU1fQ09ERV9TVEFS VChlbnRyeV9JTlQ4MF9jb21wYXQpCiAJLyoKIAkgKiBJbnRlcnJ1cHRzIGFyZSBvZmYgb24gZW50 cnkuCiAJICovCkBAIC00MTQsNCArNDE0LDQgQEAgRU5UUlkoZW50cnlfSU5UODBfY29tcGF0KQog CS8qIEdvIGJhY2sgdG8gdXNlciBtb2RlLiAqLwogCVRSQUNFX0lSUVNfT04KIAlqbXAJc3dhcGdz X3Jlc3RvcmVfcmVnc19hbmRfcmV0dXJuX3RvX3VzZXJtb2RlCi1FTkQoZW50cnlfSU5UODBfY29t cGF0KQorU1lNX0NPREVfRU5EKGVudHJ5X0lOVDgwX2NvbXBhdCkKZGlmZiAtLWdpdCBhL2FyY2gv eDg2L2tlcm5lbC9mdHJhY2VfNjQuUyBiL2FyY2gveDg2L2tlcm5lbC9mdHJhY2VfNjQuUwppbmRl eCBiNTBmYmI0MDU3NjMuLjE0MTM0MWVhYTI2NyAxMDA2NDQKLS0tIGEvYXJjaC94ODYva2VybmVs L2Z0cmFjZV82NC5TCisrKyBiL2FyY2gveDg2L2tlcm5lbC9mdHJhY2VfNjQuUwpAQCAtMzE5LDcg KzMxOSw3IEBAIEVOVFJZKGZ0cmFjZV9ncmFwaF9jYWxsZXIpCiAJcmV0cQogRU5EUFJPQyhmdHJh Y2VfZ3JhcGhfY2FsbGVyKQogCi1FTlRSWShyZXR1cm5fdG9faGFuZGxlcikKK1NZTV9DT0RFX1NU QVJUKHJldHVybl90b19oYW5kbGVyKQogCVVOV0lORF9ISU5UX0VNUFRZCiAJc3VicSAgJDI0LCAl cnNwCiAKQEAgLTMzNSw1ICszMzUsNSBAQCBFTlRSWShyZXR1cm5fdG9faGFuZGxlcikKIAltb3Zx ICglcnNwKSwgJXJheAogCWFkZHEgJDI0LCAlcnNwCiAJSk1QX05PU1BFQyAlcmRpCi1FTkQocmV0 dXJuX3RvX2hhbmRsZXIpCitTWU1fQ09ERV9FTkQocmV0dXJuX3RvX2hhbmRsZXIpCiAjZW5kaWYK ZGlmZiAtLWdpdCBhL2FyY2gveDg2L3hlbi94ZW4tYXNtXzY0LlMgYi9hcmNoL3g4Ni94ZW4veGVu LWFzbV82NC5TCmluZGV4IGE2OWExNzFmN2NlYS4uNWEzZjVjMThjZDBjIDEwMDY0NAotLS0gYS9h cmNoL3g4Ni94ZW4veGVuLWFzbV82NC5TCisrKyBiL2FyY2gveDg2L3hlbi94ZW4tYXNtXzY0LlMK QEAgLTE5LDExICsxOSwxMSBAQAogI2luY2x1ZGUgPGxpbnV4L2xpbmthZ2UuaD4KIAogLm1hY3Jv IHhlbl9wdl90cmFwIG5hbWUKLUVOVFJZKHhlbl9cbmFtZSkKK1NZTV9DT0RFX1NUQVJUKHhlbl9c bmFtZSkKIAlwb3AgJXJjeAogCXBvcCAlcjExCiAJam1wICBcbmFtZQotRU5EKHhlbl9cbmFtZSkK K1NZTV9DT0RFX0VORCh4ZW5fXG5hbWUpCiAuZW5kbQogCiB4ZW5fcHZfdHJhcCBkaXZpZGVfZXJy b3IKQEAgLTU2LDcgKzU2LDcgQEAgeGVuX3B2X3RyYXAgZW50cnlfSU5UODBfY29tcGF0CiB4ZW5f cHZfdHJhcCBoeXBlcnZpc29yX2NhbGxiYWNrCiAKIAlfX0lOSVQKLUVOVFJZKHhlbl9lYXJseV9p ZHRfaGFuZGxlcl9hcnJheSkKK1NZTV9DT0RFX1NUQVJUKHhlbl9lYXJseV9pZHRfaGFuZGxlcl9h cnJheSkKIAlpID0gMAogCS5yZXB0IE5VTV9FWENFUFRJT05fVkVDVE9SUwogCXBvcCAlcmN4CkBA IC02NSw3ICs2NSw3IEBAIEVOVFJZKHhlbl9lYXJseV9pZHRfaGFuZGxlcl9hcnJheSkKIAlpID0g aSArIDEKIAkuZmlsbCB4ZW5fZWFybHlfaWR0X2hhbmRsZXJfYXJyYXkgKyBpKlhFTl9FQVJMWV9J RFRfSEFORExFUl9TSVpFIC0gLiwgMSwgMHhjYwogCS5lbmRyCi1FTkQoeGVuX2Vhcmx5X2lkdF9o YW5kbGVyX2FycmF5KQorU1lNX0NPREVfRU5EKHhlbl9lYXJseV9pZHRfaGFuZGxlcl9hcnJheSkK IAlfX0ZJTklUCiAKIGh5cGVyY2FsbF9pcmV0ID0gaHlwZXJjYWxsX3BhZ2UgKyBfX0hZUEVSVklT T1JfaXJldCAqIDMyCmRpZmYgLS1naXQgYS9hcmNoL3g4Ni94ZW4veGVuLWhlYWQuUyBiL2FyY2gv eDg2L3hlbi94ZW4taGVhZC5TCmluZGV4IDUwNzdlYWQ1ZTU5Yy4uMzI2MDZlZWVjMDUzIDEwMDY0 NAotLS0gYS9hcmNoL3g4Ni94ZW4veGVuLWhlYWQuUworKysgYi9hcmNoL3g4Ni94ZW4veGVuLWhl YWQuUwpAQCAtMjIsNyArMjIsNyBAQAogCiAjaWZkZWYgQ09ORklHX1hFTl9QVgogCV9fSU5JVAot RU5UUlkoc3RhcnR1cF94ZW4pCitTWU1fQ09ERV9TVEFSVChzdGFydHVwX3hlbikKIAlVTldJTkRf SElOVF9FTVBUWQogCWNsZAogCkBAIC01MiwxMyArNTIsMTMgQEAgRU5UUlkoc3RhcnR1cF94ZW4p CiAjZW5kaWYKIAogCWptcCB4ZW5fc3RhcnRfa2VybmVsCi1FTkQoc3RhcnR1cF94ZW4pCitTWU1f Q09ERV9FTkQoc3RhcnR1cF94ZW4pCiAJX19GSU5JVAogI2VuZGlmCiAKIC5wdXNoc2VjdGlvbiAu dGV4dAogCS5iYWxpZ24gUEFHRV9TSVpFCi1FTlRSWShoeXBlcmNhbGxfcGFnZSkKK1NZTV9DT0RF X1NUQVJUKGh5cGVyY2FsbF9wYWdlKQogCS5yZXB0IChQQUdFX1NJWkUgLyAzMikKIAkJVU5XSU5E X0hJTlRfRU1QVFkKIAkJLnNraXAgMzIKQEAgLTY5LDcgKzY5LDcgQEAgRU5UUlkoaHlwZXJjYWxs X3BhZ2UpCiAJLnR5cGUgeGVuX2h5cGVyY2FsbF8jI24sIEBmdW5jdGlvbjsgLnNpemUgeGVuX2h5 cGVyY2FsbF8jI24sIDMyCiAjaW5jbHVkZSA8YXNtL3hlbi1oeXBlcmNhbGxzLmg+CiAjdW5kZWYg SFlQRVJDQUxMCi1FTkQoaHlwZXJjYWxsX3BhZ2UpCitTWU1fQ09ERV9FTkQoaHlwZXJjYWxsX3Bh Z2UpCiAucG9wc2VjdGlvbgogCiAJRUxGTk9URShYZW4sIFhFTl9FTEZOT1RFX0dVRVNUX09TLCAg ICAgICAuYXNjaXogImxpbnV4IikKLS0gCjIuMTYuMwoKCl9fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fClhlbi1kZXZlbCBtYWlsaW5nIGxpc3QKWGVuLWRldmVs QGxpc3RzLnhlbnByb2plY3Qub3JnCmh0dHBzOi8vbGlzdHMueGVucHJvamVjdC5vcmcvbWFpbG1h bi9saXN0aW5mby94ZW4tZGV2ZWw=