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From: Andi Kleen <ak@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [patch V11 05/16] SSB 5
Date: Thu, 10 May 2018 12:08:50 -0700	[thread overview]
Message-ID: <20180510190850.GE13616@tassilo.jf.intel.com> (raw)
In-Reply-To: <20180510183058.GJ27358@char.us.oracle.com>

On Thu, May 10, 2018 at 02:30:58PM -0400, speck for Konrad Rzeszutek Wilk wrote:
> On Thu, May 10, 2018 at 10:52:57AM -0700, speck for Andi Kleen wrote:
> > Hi,
> > 
> > I went over this patch again and I'm not sure i understand
> > how it works.
> > 
> > 
> > On Wed, May 02, 2018 at 11:51:07PM +0200, speck for Thomas Gleixner wrote:
> > > --- a/arch/x86/kvm/vmx.c
> > > +++ b/arch/x86/kvm/vmx.c
> > > @@ -9720,8 +9720,7 @@ static void __noclone vmx_vcpu_run(struc
> > >  	 * is no need to worry about the conditional branch over the wrmsr
> > >  	 * being speculatively taken.
> > >  	 */
> > > -	if (vmx->spec_ctrl)
> > > -		native_wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
> > > +	x86_spec_ctrl_set_guest(vmx->spec_ctrl);
> > >  
> > >  	vmx->__launched = vmx->loaded_vmcs->launched;
> > >  
> > > @@ -9869,8 +9868,7 @@ static void __noclone vmx_vcpu_run(struc
> > >  	if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
> > >  		vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
> > >  
> > > -	if (vmx->spec_ctrl)
> > > -		native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
> > > +	x86_spec_ctrl_restore_host(vmx->spec_ctrl);
> > 
> > So we assume that vmx->spec_ctrl is always the correct value of the guest.
> > 
> > 
> > But vmx_set_msr does
> 
> .. only if we intercept it.
> > 
> > 	        vmx->spec_ctrl = data;
> > 
> >                 if (!data)
> >                         break;
> > 
> >                 /*
> >                  * For non-nested:
> >                  * When it's written (to non-zero) for the first time, pass
> >                  * it through.
> >                  *
> >                  * For nested:
> >                  * The handling of the MSR bitmap for L2 guests is done in
> >                  * nested_vmx_merge_msr_bitmap. We should not touch the
> >                  * vmcs02.msr_bitmap here since it gets completely overwritten
> >                  * in the merging. We update the vmcs01 here for L1 as well
> >                  * since it will end up touching the MSR anyway now.
> >                  */
> >                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
> >                                               MSR_IA32_SPEC_CTRL,
> >                                               MSR_TYPE_RW);
> > 
> > That means only the value of the first write in the guest is saved in vmx->spec_ctrl.
> > 
> > But what happens when a later write is different from the first write?
> 
> This code:
> 
>   	if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
>   		vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
> 
> Would read it on the VMEXITs.

Thanks. I missed that. Good that it works.

Why don't we use the msr save/restore lists for that? That would likely
be faster than a manual msr accesses.

-Andi

  reply	other threads:[~2018-05-10 19:08 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-02 21:51 [patch V11 00/16] SSB 0 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 01/16] SSB 1 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 02/16] SSB 2 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 03/16] SSB 3 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 04/16] SSB 4 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 05/16] SSB 5 Thomas Gleixner
2018-05-10 17:52   ` [MODERATED] " Andi Kleen
2018-05-10 18:30     ` Konrad Rzeszutek Wilk
2018-05-10 19:08       ` Andi Kleen [this message]
2018-05-10 21:22         ` Konrad Rzeszutek Wilk
2018-05-10 22:25           ` Andi Kleen
2018-05-10 23:50             ` Konrad Rzeszutek Wilk
2018-05-11 16:11               ` Andi Kleen
2018-05-16  7:55               ` Paolo Bonzini
2018-05-16 13:52                 ` Konrad Rzeszutek Wilk
2018-05-02 21:51 ` [patch V11 06/16] SSB 6 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 07/16] SSB 7 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 08/16] SSB 8 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 09/16] SSB 9 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 10/16] SSB 10 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 11/16] SSB 11 Thomas Gleixner
2018-05-04 20:58   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-02 21:51 ` [patch V11 12/16] SSB 12 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 13/16] SSB 13 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 14/16] SSB 14 Thomas Gleixner
2018-05-03  7:19   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-03  7:31     ` Thomas Gleixner
2018-05-03  7:22   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-02 21:51 ` [patch V11 15/16] SSB 15 Thomas Gleixner
2018-05-03  7:21   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-02 21:51 ` [patch V11 16/16] SSB 16 Thomas Gleixner
2018-05-02 23:21 ` [patch V11 00/16] SSB 0 Thomas Gleixner
2018-05-03  4:27 ` [MODERATED] Encrypted Message Tim Chen
2018-05-03  6:10   ` [MODERATED] Re: [patch V11 00/16] SSB 0 Ingo Molnar
2018-05-03  6:30   ` Thomas Gleixner

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