[MODERATED] Re: [PATCH v4 1/8] L1TFv4 1

From: Andi Kleen <ak@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v4 1/8] L1TFv4 1
Date: Thu, 10 May 2018 16:18:04 -0700	[thread overview]
Message-ID: <20180510231804.GJ13616@tassilo.jf.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.21.1805110054570.2101@nanos.tec.linutronix.de>

> > -/* 44=32+12, the limit we can fit into an unsigned long pfn */
> > -#define __PHYSICAL_MASK_SHIFT	44
> > +/*
> > + * This is beyond the 44 bit limit imposed by the 32bit long pfns,
> > + * but we need the full mask to make sure inverted PROT_NONE
> > + * entries have all the host bits set in a guest.
> > + * The real limit is still 44 bits.
> > + */
> > +#define __PHYSICAL_MASK_SHIFT	52
> >  #define __VIRTUAL_MASK_SHIFT	32
> 
> Are you really sure that this does not have unwanted side effects in any
> (indirect) user of __PHYSICAL_MASK_SHIFT ? If yes, please indicate so in
> the changelog.

Yes I did an audit. Will indicate.

It's safe because these bits can never be set to non 0 because all PTEs
are created from unsigned long PFNs.

-Andi