From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v4,3/6] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings From: Wen He Message-Id: <20180514120307.15592-3-wen.he_1@nxp.com> Date: Mon, 14 May 2018 20:03:04 +0800 To: vinod.koul@intel.com, dmaengine@vger.kernel.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, leoyang.li@nxp.com, jiafei.pan@nxp.com, jiaheng.fan@nxp.com, Wen He List-ID: RG9jdW1lbnQgdGhlIGRldmljZXRyZWUgYmluZGluZ3MgZm9yIE5YUCBMYXllcnNjYXBlIHFETUEg Y29udHJvbGxlcgp3aGljaCBjb3VsZCBiZSBmb3VuZCBvbiBOWFAgUW9ySVEgTGF5ZXJzY2FwZSBT b0NzLgoKU2lnbmVkLW9mZi1ieTogV2VuIEhlIDx3ZW4uaGVfMUBueHAuY29tPgotLS0KY2hhbmdl IGluIHY0OgoJLSBSZXdyaXRlIHRoZSBiaW5kaW5ncyBkb2N1bWVudCB0aGF0IGZvbGxvd3MgZ2Vu ZXJpYyBETUEgYmluZGluZ3MgZmlsZQoKY2hhbmdlIGluIHYzOgoJLSBubyBjaGFuZ2UKCmNoYW5n ZSBpbiB2MjoKCS0gUmVtb3ZlIGluZGVudGF0aW9uCgktIEFkZCAiU2hvdWxkIGJlIiBiZWZvcmUg J2ZzbCxsczEwMjFhLXFkbWEnCgktIFJlcGxhY2UgJ2NoYW5uZWxzJyBieSAnZG1hLWNoYW5uZWxz JwoJLSBSZXBsYWNlICdxZG1hQDgzOTAwMDAnIGJ5ICdkbWEtY29udHJvbGxlckA4MzkwMDAwJwoK IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kbWEvZnNsLXFkbWEudHh0IHwgICA0 MSArKysrKysrKysrKysrKysrKysrKwogMSBmaWxlcyBjaGFuZ2VkLCA0MSBpbnNlcnRpb25zKCsp LCAwIGRlbGV0aW9ucygtKQogY3JlYXRlIG1vZGUgMTAwNjQ0IERvY3VtZW50YXRpb24vZGV2aWNl dHJlZS9iaW5kaW5ncy9kbWEvZnNsLXFkbWEudHh0CgpkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlv bi9kZXZpY2V0cmVlL2JpbmRpbmdzL2RtYS9mc2wtcWRtYS50eHQgYi9Eb2N1bWVudGF0aW9uL2Rl dmljZXRyZWUvYmluZGluZ3MvZG1hL2ZzbC1xZG1hLnR4dApuZXcgZmlsZSBtb2RlIDEwMDY0NApp bmRleCAwMDAwMDAwLi4zNjhjNGU3Ci0tLSAvZGV2L251bGwKKysrIGIvRG9jdW1lbnRhdGlvbi9k ZXZpY2V0cmVlL2JpbmRpbmdzL2RtYS9mc2wtcWRtYS50eHQKQEAgLTAsMCArMSw0MSBAQAorTlhQ IExheWVyc2NhcGUgU29DIHFETUEgQ29udHJvbGxlcgorPT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PQorCitUaGlzIGRldmljZSBmb2xsb3dzIHRoZSBnZW5lcmljIERNQSBiaW5kaW5n cyBkZWZpbmVkIGluIGRtYS9kbWEudHh0LgorCitSZXF1aXJlZCBwcm9wZXJ0aWVzOgorCistIGNv bXBhdGlibGU6CQlNdXN0IGJlIG9uZSBvZgorCQkJICJmc2wsbHMxMDIxYS1xZG1hIjogZm9yIExT MTAyMUEgQm9hcmQKKwkJCSAiZnNsLGxzMTA0M2EtcWRtYSI6IGZvciBsczEwNDNBIEJvYXJkCisJ CQkgImZzbCxsczEwNDZhLXFkbWEiOiBmb3IgbHMxMDQ2QSBCb2FyZAorLSByZWc6CQkJU2hvdWxk IGNvbnRhaW4gdGhlIHJlZ2lzdGVyJ3MgYmFzZSBhZGRyZXNzIGFuZCBsZW5ndGguCistIGludGVy cnVwdHM6CQlTaG91bGQgY29udGFpbiBhIHJlZmVyZW5jZSB0byB0aGUgaW50ZXJydXB0IHVzZWQg YnkgdGhpcworCQkJZGV2aWNlLgorLSBpbnRlcnJ1cHQtbmFtZXM6CVNob3VsZCBjb250YWluIGlu dGVycnVwdCBuYW1lczoKKwkJCSAicWRtYS1lcnJvciI6IHRoZSBlcnJvciBpbnRlcnJ1cHQKKwkJ CSAicWRtYS1xdWV1ZSI6IHRoZSBxdWV1ZSBpbnRlcnJ1cHQKKy0gcXVldWVzOgkJU2hvdWxkIGNv bnRhaW4gbnVtYmVyIG9mIHF1ZXVlcyBzdXBwb3J0ZWQuCisKK09wdGlvbmFsIHByb3BlcnRpZXM6 CisKKy0gZG1hLWNoYW5uZWxzOgkJTnVtYmVyIG9mIERNQSBjaGFubmVscyBzdXBwb3J0ZWQgYnkg dGhlIGNvbnRyb2xsZXIuCistIGJpZy1lbmRpYW46CQlJZiBwcmVzZW50IHJlZ2lzdGVycyBhbmQg aGFyZHdhcmUgc2NhdHRlci9nYXRoZXIgZGVzY3JpcHRvcnMKKwkJCW9mIHRoZSBxRE1BIGFyZSBp bXBsZW1lbnRlZCBpbiBiaWcgZW5kaWFuIG1vZGUsIG90aGVyd2lzZSBpbiBsaXR0bGUKKwkJCW1v ZGUuCisKK0V4YW1wbGVzOgorCisJcWRtYTogZG1hLWNvbnRyb2xsZXJAODM5MDAwMCB7CisJCWNv bXBhdGlibGUgPSAiZnNsLGxzMTAyMWEtcWRtYSI7CisJCXJlZyA9IDwweDAgMHg4Mzk4MDAwIDB4 MCAweDIwMDAgLyogQ29udHJvbGxlciByZWdpc3RlcnMgKi8KKwkJICAgICAgIDB4MCAweDgzOWEw MDAgMHgwIDB4MjAwMD47IC8qIEJsb2NrIHJlZ2lzdGVycyAqLworCQlpbnRlcnJ1cHRzID0gPEdJ Q19TUEkgMTg1IElSUV9UWVBFX0xFVkVMX0hJR0g+LAorCQkJCTxHSUNfU1BJIDc2IElSUV9UWVBF X0xFVkVMX0hJR0g+OworCQlpbnRlcnJ1cHQtbmFtZXMgPSAicWRtYS1lcnJvciIsICJxZG1hLXF1 ZXVlIjsKKwkJZG1hLWNoYW5uZWxzID0gPDg+OworCQlxdWV1ZXMgPSA8Mj47CisJCWJpZy1lbmRp YW47CisJfTsKKworRE1BIGNsaWVudHMgbXVzdCB1c2UgdGhlIGZvcm1hdCBkZXNjcmliZWQgaW4g ZG1hL2RtYS50eHQgZmlsZS4K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-dm3nam03on0121.outbound.protection.outlook.com ([104.47.41.121]:5381 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752936AbeENMEY (ORCPT ); Mon, 14 May 2018 08:04:24 -0400 From: Wen He Subject: [v4 3/6] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Date: Mon, 14 May 2018 20:03:04 +0800 Message-ID: <20180514120307.15592-3-wen.he_1@nxp.com> In-Reply-To: <20180514120307.15592-1-wen.he_1@nxp.com> References: <20180514120307.15592-1-wen.he_1@nxp.com> MIME-Version: 1.0 Content-Type: text/plain Sender: devicetree-owner@vger.kernel.org To: vinod.koul@intel.com, dmaengine@vger.kernel.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, leoyang.li@nxp.com, jiafei.pan@nxp.com, jiaheng.fan@nxp.com, Wen He List-ID: Document the devicetree bindings for NXP Layerscape qDMA controller which could be found on NXP QorIQ Layerscape SoCs. Signed-off-by: Wen He --- change in v4: - Rewrite the bindings document that follows generic DMA bindings file change in v3: - no change change in v2: - Remove indentation - Add "Should be" before 'fsl,ls1021a-qdma' - Replace 'channels' by 'dma-channels' - Replace 'qdma@8390000' by 'dma-controller@8390000' Documentation/devicetree/bindings/dma/fsl-qdma.txt | 41 ++++++++++++++++++++ 1 files changed, 41 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt new file mode 100644 index 0000000..368c4e7 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt @@ -0,0 +1,41 @@ +NXP Layerscape SoC qDMA Controller +================================== + +This device follows the generic DMA bindings defined in dma/dma.txt. + +Required properties: + +- compatible: Must be one of + "fsl,ls1021a-qdma": for LS1021A Board + "fsl,ls1043a-qdma": for ls1043A Board + "fsl,ls1046a-qdma": for ls1046A Board +- reg: Should contain the register's base address and length. +- interrupts: Should contain a reference to the interrupt used by this + device. +- interrupt-names: Should contain interrupt names: + "qdma-error": the error interrupt + "qdma-queue": the queue interrupt +- queues: Should contain number of queues supported. + +Optional properties: + +- dma-channels: Number of DMA channels supported by the controller. +- big-endian: If present registers and hardware scatter/gather descriptors + of the qDMA are implemented in big endian mode, otherwise in little + mode. + +Examples: + + qdma: dma-controller@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8398000 0x0 0x2000 /* Controller registers */ + 0x0 0x839a000 0x0 0x2000>; /* Block registers */ + interrupts = , + ; + interrupt-names = "qdma-error", "qdma-queue"; + dma-channels = <8>; + queues = <2>; + big-endian; + }; + +DMA clients must use the format described in dma/dma.txt file. -- 1.7.1