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From: Eduardo Habkost <ehabkost@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <rth@twiddle.net>,
	Eduardo Habkost <ehabkost@redhat.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	qemu-devel@nongnu.org, "Michael S. Tsirkin" <mst@redhat.com>,
	Boqun Feng <boqun.feng@intel.com>
Subject: [Qemu-devel] [PULL 1/7] i386: add KnightsMill cpu model
Date: Tue, 15 May 2018 18:54:30 -0300	[thread overview]
Message-ID: <20180515215436.6457-2-ehabkost@redhat.com> (raw)
In-Reply-To: <20180515215436.6457-1-ehabkost@redhat.com>

From: Boqun Feng <boqun.feng@intel.com>

A new cpu model called "KnightsMill" is added to model Knights Mill
processors.  Compared to "Skylake-Server" cpu model, the following
features are added:

	avx512_4vnniw avx512_4fmaps avx512pf avx512er avx512_vpopcntdq

and the following features are removed:

	pcid invpcid clflushopt avx512dq avx512bw clwb smap rtm mpx
	xsavec xgetbv1 hle

Signed-off-by: Boqun Feng <boqun.feng@intel.com>
Message-Id: <20180320000821.8337-1-boqun.feng@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 target/i386/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b0a1c629a3..52fd35b6a1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1839,6 +1839,48 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .xlevel = 0x80000008,
         .model_id = "Intel Xeon Processor (Skylake, IBRS)",
     },
+    {
+        .name = "KnightsMill",
+        .level = 0xd,
+        .vendor = CPUID_VENDOR_INTEL,
+        .family = 6,
+        .model = 133,
+        .stepping = 0,
+        .features[FEAT_1_EDX] =
+            CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
+            CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
+            CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
+            CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
+            CPUID_PSE | CPUID_DE | CPUID_FP87,
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
+            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+            CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+            CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
+            CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
+            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
+            CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
+            CPUID_7_0_EBX_AVX512ER,
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT,
+        .features[FEAT_6_EAX] =
+            CPUID_6_EAX_ARAT,
+        .xlevel = 0x80000008,
+        .model_id = "Intel Xeon Phi Processor (Knights Mill)",
+    },
     {
         .name = "Opteron_G1",
         .level = 5,
-- 
2.14.3

  reply	other threads:[~2018-05-15 21:55 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-15 21:54 [Qemu-devel] [PULL 0/7] x86 queue, 2018-05-15 Eduardo Habkost
2018-05-15 21:54 ` Eduardo Habkost [this message]
2018-05-15 21:54 ` [Qemu-devel] [PULL 2/7] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 3/7] i386: Helpers to encode cache information consistently Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 4/7] i386: Add cache information in X86CPUDefinition Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 5/7] i386: Initialize cache information for EPYC family processors Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 6/7] pc: add 2.13 machine types Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 7/7] i386: Add new property to control cache info Eduardo Habkost
2018-05-17 10:09 ` [Qemu-devel] [PULL 0/7] x86 queue, 2018-05-15 Peter Maydell

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