From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from aserp2120.oracle.com ([141.146.126.78]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fJ7NF-0006mN-MA for speck@linutronix.de; Thu, 17 May 2018 03:06:30 +0200 Received: from pps.filterd (aserp2120.oracle.com [127.0.0.1]) by aserp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w4H0p79q122878 for ; Thu, 17 May 2018 01:06:22 GMT Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by aserp2120.oracle.com with ESMTP id 2hx29w762t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Thu, 17 May 2018 01:06:22 +0000 Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w4H16LEx030892 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Thu, 17 May 2018 01:06:21 GMT Received: from abhmp0006.oracle.com (abhmp0006.oracle.com [141.146.116.12]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id w4H16L81031739 for ; Thu, 17 May 2018 01:06:21 GMT Date: Wed, 16 May 2018 21:06:20 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [patch 03/15] SSB updates V17 3 Message-ID: <20180517010620.GB10272@char.us.oracle.com> References: <20180516135132.687640705@linutronix.de> <20180516135209.547142953@linutronix.de> MIME-Version: 1.0 In-Reply-To: <20180516135209.547142953@linutronix.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, May 16, 2018 at 03:51:35PM +0200, speck for Thomas Gleixner wrote: > Subject: [patch 03/15] x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRS > From: Thomas Gleixner > > The availability of the SPEC_CTRL MSR is enumerated by a CPUID bit on > Intel and implied by IBRS or STIBP support on AMD. That's just confusing > and in case an AMD CPU has IBRS not supported because the underlying > problem has been fixed but has another bit valid in the SPEC_CTRL MSR, > the thing falls apart. > > Add a synthetic feature bit X86_FEATURE_MSR_SPEC_CTRL to denote the > availability on both Intel and AMD. > > While at it replace the boot_cpu_has() checks with static_cpu_has() where > possible. This prevents late microcode loading from exposing SPEC_CTRL, but > late loading is already very limited as it does not reevaluate the > mitigation options and other bits and pieces. Having static_cpu_has() is > the simplest and least fragile solution. > > Signed-off-by: Thomas Gleixner > Reviewed-by: Borislav Petkov Reviewed-by: Konrad Rzeszutek Wilk