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x-vs=clean score=-100 state=0 X-ME-VSCategory: clean X-CM-Envelope: MS4wfFMQz6D4vYE2mgAbCDNOjsPqpJ4v+fewLITt21Y4Llv0k7YEDWsYDJNKxR7awaGWV3kntz1nyG6/nQ7y1kssiS+C6oVIhXNStTOlvz112+to0AL3nSLu 70ajTC6B4/YwlON5B8OlSVS3S544r9aG1AURUIkO1bCog1lBRUnCoIWV5cfg2wRZEwag++cHDQ4vzcdzD6rUBnxKtK0irhLHLue+E7iFWWRoGysSwk0aJBdd X-CM-Analysis: v=2.3 cv=JLoVTfCb c=1 sm=1 tr=0 a=UK1r566ZdBxH71SXbqIOeA==:117 a=UK1r566ZdBxH71SXbqIOeA==:17 a=kj9zAlcOel0A:10 a=VUJBJC2UJ8kA:10 a=VwQbUJbxAAAA:8 a=7CQSdrXTAAAA:8 a=5hbFD1BkjCuMjG_J0ygA:9 a=CjuIK1q_8ugA:10 a=AjGcO6oz07-iQ99wixmX:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-ME-CMScore: 0 X-ME-CMCategory: none Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751017AbeEQJBg (ORCPT ); Thu, 17 May 2018 05:01:36 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:35565 "EHLO out1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750779AbeEQJBd (ORCPT ); Thu, 17 May 2018 05:01:33 -0400 X-ME-Proxy: X-ME-Proxy: X-ME-Proxy: X-ME-Proxy: X-ME-Proxy: X-ME-Proxy: X-ME-Sender: Date: Thu, 17 May 2018 11:01:15 +0200 From: Greg KH To: Suzuki K Poulose Cc: stable@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, dave.martin@arm.com Subject: Re: [PATCH 2/2] [stable 4.4] arm64: Add work around for Arm Cortex-A55 Erratum 1024718 Message-ID: <20180517090115.GE25318@kroah.com> References: <1526295664-22187-1-git-send-email-suzuki.poulose@arm.com> <1526295664-22187-2-git-send-email-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1526295664-22187-2-git-send-email-suzuki.poulose@arm.com> User-Agent: Mutt/1.9.5 (2018-04-13) Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Mon, May 14, 2018 at 12:01:04PM +0100, Suzuki K Poulose wrote: > commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream > > Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer > from an erratum 1024718, which causes incorrect updates when DBM/AP > bits in a page table entry is modified without a break-before-make > sequence. The work around is to disable the hardware DBM feature > on the affected cores. The hardware Access Flag management features > is not affected. > > The hardware DBM feature is a non-conflicting capability, i.e, the > kernel could handle cores using the feature and those without having > the features running at the same time. So this work around is detected > at early boot time, rather than delaying it until the CPUs are brought > up into the kernel with MMU turned on. This also avoids other complexities > with late CPUs turning online, with or without the hardware DBM features. > > Cc: stable@vger.kernel.org # v4.4 > Cc: Catalin Marinas > Cc: Mark Rutland > Cc: Will Deacon > Signed-off-by: Suzuki K Poulose > --- > Note: The upstream commit is on top of a reworked capability > infrastructure for arm64 heterogeneous systems, which allows > delaying the CPU model checks. This backport is based on the > original version of the patch [0], which checks the affected > CPU models during the early boot. > > [0] https://lkml.kernel.org/r/20180116102323.3470-1-suzuki.poulose@arm.com Thanks for these, now queued up. greg k-h From mboxrd@z Thu Jan 1 00:00:00 1970 From: greg@kroah.com (Greg KH) Date: Thu, 17 May 2018 11:01:15 +0200 Subject: [PATCH 2/2] [stable 4.4] arm64: Add work around for Arm Cortex-A55 Erratum 1024718 In-Reply-To: <1526295664-22187-2-git-send-email-suzuki.poulose@arm.com> References: <1526295664-22187-1-git-send-email-suzuki.poulose@arm.com> <1526295664-22187-2-git-send-email-suzuki.poulose@arm.com> Message-ID: <20180517090115.GE25318@kroah.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, May 14, 2018 at 12:01:04PM +0100, Suzuki K Poulose wrote: > commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream > > Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer > from an erratum 1024718, which causes incorrect updates when DBM/AP > bits in a page table entry is modified without a break-before-make > sequence. The work around is to disable the hardware DBM feature > on the affected cores. The hardware Access Flag management features > is not affected. > > The hardware DBM feature is a non-conflicting capability, i.e, the > kernel could handle cores using the feature and those without having > the features running at the same time. So this work around is detected > at early boot time, rather than delaying it until the CPUs are brought > up into the kernel with MMU turned on. This also avoids other complexities > with late CPUs turning online, with or without the hardware DBM features. > > Cc: stable at vger.kernel.org # v4.4 > Cc: Catalin Marinas > Cc: Mark Rutland > Cc: Will Deacon > Signed-off-by: Suzuki K Poulose > --- > Note: The upstream commit is on top of a reworked capability > infrastructure for arm64 heterogeneous systems, which allows > delaying the CPU model checks. This backport is based on the > original version of the patch [0], which checks the affected > CPU models during the early boot. > > [0] https://lkml.kernel.org/r/20180116102323.3470-1-suzuki.poulose at arm.com Thanks for these, now queued up. greg k-h