From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752089AbeEQScC (ORCPT ); Thu, 17 May 2018 14:32:02 -0400 Received: from mx2.suse.de ([195.135.220.15]:35285 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751017AbeEQScB (ORCPT ); Thu, 17 May 2018 14:32:01 -0400 Date: Thu, 17 May 2018 20:31:44 +0200 From: Borislav Petkov To: "Ghannam, Yazen" Cc: Johannes Hirte , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" Subject: [PATCH 2/2] x86/MCE/AMD: Read MCx_MISC block addresses on any CPU Message-ID: <20180517183144.GB24312@pd.tnic> References: <20180414004230.GA2033@probook> <20180416115624.GA1543@probook> <20180515093953.GA1746@probook> <20180516224641.GA31929@pd.tnic> <20180517064930.GA26421@probook> <20180517104124.GA25595@pd.tnic> <20180517134415.GC27738@pd.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.3 (2018-01-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Borislav Petkov We used rdmsr_safe_on_cpu() to make sure we're reading the proper CPU's MISC block addresses. However, that caused trouble with CPU hotplug due to the _on_cpu() helper issuing an IPI while IRQs are disabled. But we don't have to do that: the block addresses are the same on any CPU so we can read them on any CPU. (What practically happens is, we read them on the BSP and cache them, and for later reads, we service them from the cache). Suggested-by: Yazen Ghannam Signed-off-by: Borislav Petkov --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index c8e038800591..f591b01930db 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -436,8 +436,7 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) wrmsr(MSR_CU_DEF_ERR, low, high); } -static u32 smca_get_block_address(unsigned int cpu, unsigned int bank, - unsigned int block) +static u32 smca_get_block_address(unsigned int bank, unsigned int block) { u32 low, high; u32 addr = 0; @@ -456,13 +455,13 @@ static u32 smca_get_block_address(unsigned int cpu, unsigned int bank, * For SMCA enabled processors, BLKPTR field of the first MISC register * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). */ - if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) + if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) goto out; if (!(low & MCI_CONFIG_MCAX)) goto out; - if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && + if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && (low & MASK_BLKPTR_LO)) addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); @@ -471,7 +470,7 @@ static u32 smca_get_block_address(unsigned int cpu, unsigned int bank, return addr; } -static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high, +static u32 get_block_address(u32 current_addr, u32 low, u32 high, unsigned int bank, unsigned int block) { u32 addr = 0, offset = 0; @@ -480,7 +479,7 @@ static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 hi return addr; if (mce_flags.smca) - return smca_get_block_address(cpu, bank, block); + return smca_get_block_address(bank, block); /* Fall back to method we used for older processors: */ switch (block) { @@ -558,7 +557,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) smca_configure(bank, cpu); for (block = 0; block < NR_BLOCKS; ++block) { - address = get_block_address(cpu, address, low, high, bank, block); + address = get_block_address(address, low, high, bank, block); if (!address) break; @@ -1175,7 +1174,7 @@ static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, if (err) goto out_free; recurse: - address = get_block_address(cpu, address, low, high, bank, ++block); + address = get_block_address(address, low, high, bank, ++block); if (!address) return 0; -- 2.17.0.391.g1f1cddd558b5 SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) -- From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [2/2] x86/MCE/AMD: Read MCx_MISC block addresses on any CPU From: Boris Petkov Message-Id: <20180517183144.GB24312@pd.tnic> Date: Thu, 17 May 2018 20:31:44 +0200 To: "Ghannam, Yazen" Cc: Johannes Hirte , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" List-ID: RnJvbTogQm9yaXNsYXYgUGV0a292IDxicEBzdXNlLmRlPgoKV2UgdXNlZCByZG1zcl9zYWZlX29u X2NwdSgpIHRvIG1ha2Ugc3VyZSB3ZSdyZSByZWFkaW5nIHRoZSBwcm9wZXIgQ1BVJ3MKTUlTQyBi bG9jayBhZGRyZXNzZXMuIEhvd2V2ZXIsIHRoYXQgY2F1c2VkIHRyb3VibGUgd2l0aCBDUFUgaG90 cGx1ZyBkdWUKdG8gdGhlIF9vbl9jcHUoKSBoZWxwZXIgaXNzdWluZyBhbiBJUEkgd2hpbGUgSVJR cyBhcmUgZGlzYWJsZWQuCgpCdXQgd2UgZG9uJ3QgaGF2ZSB0byBkbyB0aGF0OiB0aGUgYmxvY2sg YWRkcmVzc2VzIGFyZSB0aGUgc2FtZSBvbiBhbnkKQ1BVIHNvIHdlIGNhbiByZWFkIHRoZW0gb24g YW55IENQVS4gKFdoYXQgcHJhY3RpY2FsbHkgaGFwcGVucyBpcywgd2UKcmVhZCB0aGVtIG9uIHRo ZSBCU1AgYW5kIGNhY2hlIHRoZW0sIGFuZCBmb3IgbGF0ZXIgcmVhZHMsIHdlIHNlcnZpY2UKdGhl bSBmcm9tIHRoZSBjYWNoZSkuCgpTdWdnZXN0ZWQtYnk6IFlhemVuIEdoYW5uYW0gPFlhemVuLkdo YW5uYW1AYW1kLmNvbT4KU2lnbmVkLW9mZi1ieTogQm9yaXNsYXYgUGV0a292IDxicEBzdXNlLmRl PgotLS0KIGFyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZV9hbWQuYyB8IDE1ICsrKysrKyst LS0tLS0tLQogMSBmaWxlIGNoYW5nZWQsIDcgaW5zZXJ0aW9ucygrKSwgOCBkZWxldGlvbnMoLSkK CmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2VfYW1kLmMgYi9hcmNo L3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2VfYW1kLmMKaW5kZXggYzhlMDM4ODAwNTkxLi5mNTkx YjAxOTMwZGIgMTAwNjQ0Ci0tLSBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZV9hbWQu YworKysgYi9hcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2VfYW1kLmMKQEAgLTQzNiw4ICs0 MzYsNyBAQCBzdGF0aWMgdm9pZCBkZWZlcnJlZF9lcnJvcl9pbnRlcnJ1cHRfZW5hYmxlKHN0cnVj dCBjcHVpbmZvX3g4NiAqYykKIAl3cm1zcihNU1JfQ1VfREVGX0VSUiwgbG93LCBoaWdoKTsKIH0K IAotc3RhdGljIHUzMiBzbWNhX2dldF9ibG9ja19hZGRyZXNzKHVuc2lnbmVkIGludCBjcHUsIHVu c2lnbmVkIGludCBiYW5rLAotCQkJCSAgdW5zaWduZWQgaW50IGJsb2NrKQorc3RhdGljIHUzMiBz bWNhX2dldF9ibG9ja19hZGRyZXNzKHVuc2lnbmVkIGludCBiYW5rLCB1bnNpZ25lZCBpbnQgYmxv Y2spCiB7CiAJdTMyIGxvdywgaGlnaDsKIAl1MzIgYWRkciA9IDA7CkBAIC00NTYsMTMgKzQ1NSwx MyBAQCBzdGF0aWMgdTMyIHNtY2FfZ2V0X2Jsb2NrX2FkZHJlc3ModW5zaWduZWQgaW50IGNwdSwg dW5zaWduZWQgaW50IGJhbmssCiAJICogRm9yIFNNQ0EgZW5hYmxlZCBwcm9jZXNzb3JzLCBCTEtQ VFIgZmllbGQgb2YgdGhlIGZpcnN0IE1JU0MgcmVnaXN0ZXIKIAkgKiAoTUN4X01JU0MwKSBpbmRp Y2F0ZXMgcHJlc2VuY2Ugb2YgYWRkaXRpb25hbCBNSVNDIHJlZ3Mgc2V0IChNSVNDMS00KS4KIAkg Ki8KLQlpZiAocmRtc3Jfc2FmZV9vbl9jcHUoY3B1LCBNU1JfQU1ENjRfU01DQV9NQ3hfQ09ORklH KGJhbmspLCAmbG93LCAmaGlnaCkpCisJaWYgKHJkbXNyX3NhZmUoTVNSX0FNRDY0X1NNQ0FfTUN4 X0NPTkZJRyhiYW5rKSwgJmxvdywgJmhpZ2gpKQogCQlnb3RvIG91dDsKIAogCWlmICghKGxvdyAm IE1DSV9DT05GSUdfTUNBWCkpCiAJCWdvdG8gb3V0OwogCi0JaWYgKCFyZG1zcl9zYWZlX29uX2Nw dShjcHUsIE1TUl9BTUQ2NF9TTUNBX01DeF9NSVNDKGJhbmspLCAmbG93LCAmaGlnaCkgJiYKKwlp ZiAoIXJkbXNyX3NhZmUoTVNSX0FNRDY0X1NNQ0FfTUN4X01JU0MoYmFuayksICZsb3csICZoaWdo KSAmJgogCSAgICAobG93ICYgTUFTS19CTEtQVFJfTE8pKQogCQlhZGRyID0gTVNSX0FNRDY0X1NN Q0FfTUN4X01JU0N5KGJhbmssIGJsb2NrIC0gMSk7CiAKQEAgLTQ3MSw3ICs0NzAsNyBAQCBzdGF0 aWMgdTMyIHNtY2FfZ2V0X2Jsb2NrX2FkZHJlc3ModW5zaWduZWQgaW50IGNwdSwgdW5zaWduZWQg aW50IGJhbmssCiAJcmV0dXJuIGFkZHI7CiB9CiAKLXN0YXRpYyB1MzIgZ2V0X2Jsb2NrX2FkZHJl c3ModW5zaWduZWQgaW50IGNwdSwgdTMyIGN1cnJlbnRfYWRkciwgdTMyIGxvdywgdTMyIGhpZ2gs CitzdGF0aWMgdTMyIGdldF9ibG9ja19hZGRyZXNzKHUzMiBjdXJyZW50X2FkZHIsIHUzMiBsb3cs IHUzMiBoaWdoLAogCQkJICAgICB1bnNpZ25lZCBpbnQgYmFuaywgdW5zaWduZWQgaW50IGJsb2Nr KQogewogCXUzMiBhZGRyID0gMCwgb2Zmc2V0ID0gMDsKQEAgLTQ4MCw3ICs0NzksNyBAQCBzdGF0 aWMgdTMyIGdldF9ibG9ja19hZGRyZXNzKHVuc2lnbmVkIGludCBjcHUsIHUzMiBjdXJyZW50X2Fk ZHIsIHUzMiBsb3csIHUzMiBoaQogCQlyZXR1cm4gYWRkcjsKIAogCWlmIChtY2VfZmxhZ3Muc21j YSkKLQkJcmV0dXJuIHNtY2FfZ2V0X2Jsb2NrX2FkZHJlc3MoY3B1LCBiYW5rLCBibG9jayk7CisJ CXJldHVybiBzbWNhX2dldF9ibG9ja19hZGRyZXNzKGJhbmssIGJsb2NrKTsKIAogCS8qIEZhbGwg YmFjayB0byBtZXRob2Qgd2UgdXNlZCBmb3Igb2xkZXIgcHJvY2Vzc29yczogKi8KIAlzd2l0Y2gg KGJsb2NrKSB7CkBAIC01NTgsNyArNTU3LDcgQEAgdm9pZCBtY2VfYW1kX2ZlYXR1cmVfaW5pdChz dHJ1Y3QgY3B1aW5mb194ODYgKmMpCiAJCQlzbWNhX2NvbmZpZ3VyZShiYW5rLCBjcHUpOwogCiAJ CWZvciAoYmxvY2sgPSAwOyBibG9jayA8IE5SX0JMT0NLUzsgKytibG9jaykgewotCQkJYWRkcmVz cyA9IGdldF9ibG9ja19hZGRyZXNzKGNwdSwgYWRkcmVzcywgbG93LCBoaWdoLCBiYW5rLCBibG9j ayk7CisJCQlhZGRyZXNzID0gZ2V0X2Jsb2NrX2FkZHJlc3MoYWRkcmVzcywgbG93LCBoaWdoLCBi YW5rLCBibG9jayk7CiAJCQlpZiAoIWFkZHJlc3MpCiAJCQkJYnJlYWs7CiAKQEAgLTExNzUsNyAr MTE3NCw3IEBAIHN0YXRpYyBpbnQgYWxsb2NhdGVfdGhyZXNob2xkX2Jsb2Nrcyh1bnNpZ25lZCBp bnQgY3B1LCB1bnNpZ25lZCBpbnQgYmFuaywKIAlpZiAoZXJyKQogCQlnb3RvIG91dF9mcmVlOwog cmVjdXJzZToKLQlhZGRyZXNzID0gZ2V0X2Jsb2NrX2FkZHJlc3MoY3B1LCBhZGRyZXNzLCBsb3cs IGhpZ2gsIGJhbmssICsrYmxvY2spOworCWFkZHJlc3MgPSBnZXRfYmxvY2tfYWRkcmVzcyhhZGRy ZXNzLCBsb3csIGhpZ2gsIGJhbmssICsrYmxvY2spOwogCWlmICghYWRkcmVzcykKIAkJcmV0dXJu IDA7CiAK