* [PATCH] x86/speculation: Simplify the CPU bug detection logic
@ 2018-05-22 9:05 Dominik Brodowski
2018-05-23 9:01 ` [tip:x86/pti] " tip-bot for Dominik Brodowski
2018-05-23 16:33 ` [PATCH] " Konrad Rzeszutek Wilk
0 siblings, 2 replies; 4+ messages in thread
From: Dominik Brodowski @ 2018-05-22 9:05 UTC (permalink / raw)
To: konrad.wilk, tglx, mingo, bp; +Cc: x86, linux-kernel
Only CPUs which speculate can speculate. Therefore, it seems prudent
to test for cpu_no_speculation first and only then determine whether
a specific speculating CPU is susceptible to store bypass speculation.
This is underlined by all CPUs currently listed in cpu_no_speculation
were present in cpu_no_spec_store_bypass as well.
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
---
arch/x86/kernel/cpu/common.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 78decc3e3067..2fcc1fbf11b0 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -942,12 +942,8 @@ static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
{}
};
+/* Only list CPUs which speculate but are non susceptible to SSB */
static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW },
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT },
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL },
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW },
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
@@ -955,14 +951,10 @@ static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
- { X86_VENDOR_CENTAUR, 5, },
- { X86_VENDOR_INTEL, 5, },
- { X86_VENDOR_NSC, 5, },
{ X86_VENDOR_AMD, 0x12, },
{ X86_VENDOR_AMD, 0x11, },
{ X86_VENDOR_AMD, 0x10, },
{ X86_VENDOR_AMD, 0xf, },
- { X86_VENDOR_ANY, 4, },
{}
};
@@ -973,16 +965,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
- if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
- !(ia32_cap & ARCH_CAP_SSB_NO))
- setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
-
if (x86_match_cpu(cpu_no_speculation))
return;
setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
+ if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
+ !(ia32_cap & ARCH_CAP_SSB_NO))
+ setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
+
if (x86_match_cpu(cpu_no_meltdown))
return;
--
2.17.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [tip:x86/pti] x86/speculation: Simplify the CPU bug detection logic
2018-05-22 9:05 [PATCH] x86/speculation: Simplify the CPU bug detection logic Dominik Brodowski
@ 2018-05-23 9:01 ` tip-bot for Dominik Brodowski
2018-05-23 16:33 ` [PATCH] " Konrad Rzeszutek Wilk
1 sibling, 0 replies; 4+ messages in thread
From: tip-bot for Dominik Brodowski @ 2018-05-23 9:01 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, mingo, linux, tglx, hpa
Commit-ID: 8ecc4979b1bd9c94168e6fc92960033b7a951336
Gitweb: https://git.kernel.org/tip/8ecc4979b1bd9c94168e6fc92960033b7a951336
Author: Dominik Brodowski <linux@dominikbrodowski.net>
AuthorDate: Tue, 22 May 2018 11:05:39 +0200
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 23 May 2018 10:55:52 +0200
x86/speculation: Simplify the CPU bug detection logic
Only CPUs which speculate can speculate. Therefore, it seems prudent
to test for cpu_no_speculation first and only then determine whether
a specific speculating CPU is susceptible to store bypass speculation.
This is underlined by all CPUs currently listed in cpu_no_speculation
were present in cpu_no_spec_store_bypass as well.
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: bp@suse.de
Cc: konrad.wilk@oracle.com
Link: https://lkml.kernel.org/r/20180522090539.GA24668@light.dominikbrodowski.net
---
arch/x86/kernel/cpu/common.c | 22 +++++++---------------
1 file changed, 7 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 78decc3e3067..38276f58d3bf 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -942,12 +942,8 @@ static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
{}
};
+/* Only list CPUs which speculate but are non susceptible to SSB */
static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW },
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT },
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL },
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW },
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
@@ -955,14 +951,10 @@ static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
- { X86_VENDOR_CENTAUR, 5, },
- { X86_VENDOR_INTEL, 5, },
- { X86_VENDOR_NSC, 5, },
{ X86_VENDOR_AMD, 0x12, },
{ X86_VENDOR_AMD, 0x11, },
{ X86_VENDOR_AMD, 0x10, },
{ X86_VENDOR_AMD, 0xf, },
- { X86_VENDOR_ANY, 4, },
{}
};
@@ -970,6 +962,12 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
{
u64 ia32_cap = 0;
+ if (x86_match_cpu(cpu_no_speculation))
+ return;
+
+ setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
+ setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
+
if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
@@ -977,12 +975,6 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
!(ia32_cap & ARCH_CAP_SSB_NO))
setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
- if (x86_match_cpu(cpu_no_speculation))
- return;
-
- setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
- setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
-
if (x86_match_cpu(cpu_no_meltdown))
return;
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] x86/speculation: Simplify the CPU bug detection logic
2018-05-22 9:05 [PATCH] x86/speculation: Simplify the CPU bug detection logic Dominik Brodowski
2018-05-23 9:01 ` [tip:x86/pti] " tip-bot for Dominik Brodowski
@ 2018-05-23 16:33 ` Konrad Rzeszutek Wilk
2018-05-23 19:50 ` Thomas Gleixner
1 sibling, 1 reply; 4+ messages in thread
From: Konrad Rzeszutek Wilk @ 2018-05-23 16:33 UTC (permalink / raw)
To: Dominik Brodowski; +Cc: tglx, mingo, bp, x86, linux-kernel
On Tue, May 22, 2018 at 11:05:39AM +0200, Dominik Brodowski wrote:
> Only CPUs which speculate can speculate. Therefore, it seems prudent
> to test for cpu_no_speculation first and only then determine whether
> a specific speculating CPU is susceptible to store bypass speculation.
> This is underlined by all CPUs currently listed in cpu_no_speculation
> were present in cpu_no_spec_store_bypass as well.
>
> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
> ---
> arch/x86/kernel/cpu/common.c | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 78decc3e3067..2fcc1fbf11b0 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -942,12 +942,8 @@ static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
> {}
> };
>
> +/* Only list CPUs which speculate but are non susceptible to SSB */
> static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
> - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW },
> - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT },
> - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL },
> - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW },
> - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW },
> { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
> { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
> { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
> @@ -955,14 +951,10 @@ static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
> { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH },
> { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
> { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
> - { X86_VENDOR_CENTAUR, 5, },
> - { X86_VENDOR_INTEL, 5, },
> - { X86_VENDOR_NSC, 5, },
> { X86_VENDOR_AMD, 0x12, },
> { X86_VENDOR_AMD, 0x11, },
> { X86_VENDOR_AMD, 0x10, },
> { X86_VENDOR_AMD, 0xf, },
> - { X86_VENDOR_ANY, 4, },
> {}
> };
>
> @@ -973,16 +965,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
> if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
> rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
Would it make sense to move that above 'rdmsrl' and the conditional as well
to the logic below?
>
> - if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
> - !(ia32_cap & ARCH_CAP_SSB_NO))
> - setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
> -
> if (x86_match_cpu(cpu_no_speculation))
> return;
>
> setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
> setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
>
> + if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
> + !(ia32_cap & ARCH_CAP_SSB_NO))
> + setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
> +
> if (x86_match_cpu(cpu_no_meltdown))
> return;
>
> --
> 2.17.0
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] x86/speculation: Simplify the CPU bug detection logic
2018-05-23 16:33 ` [PATCH] " Konrad Rzeszutek Wilk
@ 2018-05-23 19:50 ` Thomas Gleixner
0 siblings, 0 replies; 4+ messages in thread
From: Thomas Gleixner @ 2018-05-23 19:50 UTC (permalink / raw)
To: Konrad Rzeszutek Wilk; +Cc: Dominik Brodowski, mingo, bp, x86, linux-kernel
On Wed, 23 May 2018, Konrad Rzeszutek Wilk wrote:
> > @@ -973,16 +965,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
> > if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
> > rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
>
> Would it make sense to move that above 'rdmsrl' and the conditional as well
> to the logic below?
I did that when I was applying the patch ....
Thanks,
tglx
^ permalink raw reply [flat|nested] 4+ messages in thread
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2018-05-22 9:05 [PATCH] x86/speculation: Simplify the CPU bug detection logic Dominik Brodowski
2018-05-23 9:01 ` [tip:x86/pti] " tip-bot for Dominik Brodowski
2018-05-23 16:33 ` [PATCH] " Konrad Rzeszutek Wilk
2018-05-23 19:50 ` Thomas Gleixner
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