From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Date: Tue, 22 May 2018 12:04:05 +0000 Subject: common non-cache coherent direct dma mapping ops v2 Message-Id: <20180522120430.28709-1-hch@lst.de> List-Id: References: <20180511075945.16548-1-hch@lst.de> In-Reply-To: <20180511075945.16548-1-hch@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: iommu@lists.linux-foundation.org Cc: linux-arch@vger.kernel.org, Michal Simek , Greentime Hu , Vincent Chen , linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-hexagon@vger.kernel.org, linux-m68k@lists.linux-m68k.org, nios2-dev@lists.rocketboards.org, openrisc@lists.librecores.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-xtensa@linux-xtensa.org, linux-kernel@vger.kernel.org Hi all, this series continues consolidating the dma-mapping code, with a focus on architectures that do not (always) provide cache coherence for DMA. Three architectures (arm, mips and powerpc) are still left to be converted later due to complexity of their dma ops selection. The dma-noncoherent ops calls the dma-direct ops for the actual translation of streaming mappins and allow the architecture to provide any cache flushing required for cpu to device and/or device to cpu ownership transfers. The dma coherent allocator is for now still left entirely to architecture supplied implementations due the amount of variations. Hopefully we can do some consolidation for them later on as well. A lot of architectures are currently doing very questionable things in their dma mapping routines, which are documented in the changelogs for each patch. Please review them very careful and correct me on incorrect assumptions. Because this series sits on top of three previously submitted series a git tree might be useful to actually test it. It is provided here: git://git.infradead.org/users/hch/misc.git generic-dma-noncoherent.2 Gitweb: http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/generic-dma-noncoherent.2 Changes since v1: - dropped the already merged generic, arc and c6x patches (with the map_single offset fix from Alexey Brodkin) - split various changes into smaller patches - dropped the arm-nommu changes for now - fixed a typo Changes since RFC: - fix a typo accidentally disabling the device to cpu transfer sync - fixed a few compile failures From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: common non-cache coherent direct dma mapping ops v2 Date: Tue, 22 May 2018 14:04:05 +0200 Message-ID: <20180522120430.28709-1-hch@lst.de> Cc: linux-arch@vger.kernel.org, Michal Simek , Greentime Hu , Vincent Chen , linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-c6x-dev@linux-c6x.org, linux-hexagon@vger.kernel.org, linux-m68k@lists.linux-m68k.org, nios2-dev@lists.rocketboards.org, openrisc@lists.librecores.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-xtensa@linux-xtensa.org, linux-kernel@vger.kernel.org To: iommu@lists.linux-foundation.org Return-path: List-ID: List-Id: linux-parisc.vger.kernel.org Hi all, this series continues consolidating the dma-mapping code, with a focus on architectures that do not (always) provide cache coherence for DMA. Three architectures (arm, mips and powerpc) are still left to be converted later due to complexity of their dma ops selection. The dma-noncoherent ops calls the dma-direct ops for the actual translation of streaming mappins and allow the architecture to provide any cache flushing required for cpu to device and/or device to cpu ownership transfers. The dma coherent allocator is for now still left entirely to architecture supplied implementations due the amount of variations. Hopefully we can do some consolidation for them later on as well. A lot of architectures are currently doing very questionable things in their dma mapping routines, which are documented in the changelogs for each patch. Please review them very careful and correct me on incorrect assumptions. Because this series sits on top of three previously submitted series a git tree might be useful to actually test it. It is provided here: git://git.infradead.org/users/hch/misc.git generic-dma-noncoherent.2 Gitweb: http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/generic-dma-noncoherent.2 Changes since v1: - dropped the already merged generic, arc and c6x patches (with the map_single offset fix from Alexey Brodkin) - split various changes into smaller patches - dropped the arm-nommu changes for now - fixed a typo Changes since RFC: - fix a typo accidentally disabling the device to cpu transfer sync - fixed a few compile failures From mboxrd@z Thu Jan 1 00:00:00 1970 From: hch@lst.de (Christoph Hellwig) Date: Tue, 22 May 2018 14:04:05 +0200 Subject: common non-cache coherent direct dma mapping ops v2 List-ID: Message-ID: <20180522120430.28709-1-hch@lst.de> To: linux-snps-arc@lists.infradead.org Hi all, this series continues consolidating the dma-mapping code, with a focus on architectures that do not (always) provide cache coherence for DMA. Three architectures (arm, mips and powerpc) are still left to be converted later due to complexity of their dma ops selection. The dma-noncoherent ops calls the dma-direct ops for the actual translation of streaming mappins and allow the architecture to provide any cache flushing required for cpu to device and/or device to cpu ownership transfers. The dma coherent allocator is for now still left entirely to architecture supplied implementations due the amount of variations. Hopefully we can do some consolidation for them later on as well. A lot of architectures are currently doing very questionable things in their dma mapping routines, which are documented in the changelogs for each patch. Please review them very careful and correct me on incorrect assumptions. Because this series sits on top of three previously submitted series a git tree might be useful to actually test it. It is provided here: git://git.infradead.org/users/hch/misc.git generic-dma-noncoherent.2 Gitweb: http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/generic-dma-noncoherent.2 Changes since v1: - dropped the already merged generic, arc and c6x patches (with the map_single offset fix from Alexey Brodkin) - split various changes into smaller patches - dropped the arm-nommu changes for now - fixed a typo Changes since RFC: - fix a typo accidentally disabling the device to cpu transfer sync - fixed a few compile failures From mboxrd@z Thu Jan 1 00:00:00 1970 From: hch@lst.de (Christoph Hellwig) Date: Tue, 22 May 2018 14:04:05 +0200 Subject: common non-cache coherent direct dma mapping ops v2 Message-ID: <20180522120430.28709-1-hch@lst.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi all, this series continues consolidating the dma-mapping code, with a focus on architectures that do not (always) provide cache coherence for DMA. Three architectures (arm, mips and powerpc) are still left to be converted later due to complexity of their dma ops selection. The dma-noncoherent ops calls the dma-direct ops for the actual translation of streaming mappins and allow the architecture to provide any cache flushing required for cpu to device and/or device to cpu ownership transfers. The dma coherent allocator is for now still left entirely to architecture supplied implementations due the amount of variations. Hopefully we can do some consolidation for them later on as well. A lot of architectures are currently doing very questionable things in their dma mapping routines, which are documented in the changelogs for each patch. Please review them very careful and correct me on incorrect assumptions. Because this series sits on top of three previously submitted series a git tree might be useful to actually test it. It is provided here: git://git.infradead.org/users/hch/misc.git generic-dma-noncoherent.2 Gitweb: http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/generic-dma-noncoherent.2 Changes since v1: - dropped the already merged generic, arc and c6x patches (with the map_single offset fix from Alexey Brodkin) - split various changes into smaller patches - dropped the arm-nommu changes for now - fixed a typo Changes since RFC: - fix a typo accidentally disabling the device to cpu transfer sync - fixed a few compile failures From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Date: Tue, 22 May 2018 14:04:05 +0200 Subject: [OpenRISC] common non-cache coherent direct dma mapping ops v2 Message-ID: <20180522120430.28709-1-hch@lst.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: openrisc@lists.librecores.org Hi all, this series continues consolidating the dma-mapping code, with a focus on architectures that do not (always) provide cache coherence for DMA. Three architectures (arm, mips and powerpc) are still left to be converted later due to complexity of their dma ops selection. The dma-noncoherent ops calls the dma-direct ops for the actual translation of streaming mappins and allow the architecture to provide any cache flushing required for cpu to device and/or device to cpu ownership transfers. The dma coherent allocator is for now still left entirely to architecture supplied implementations due the amount of variations. Hopefully we can do some consolidation for them later on as well. A lot of architectures are currently doing very questionable things in their dma mapping routines, which are documented in the changelogs for each patch. Please review them very careful and correct me on incorrect assumptions. Because this series sits on top of three previously submitted series a git tree might be useful to actually test it. It is provided here: git://git.infradead.org/users/hch/misc.git generic-dma-noncoherent.2 Gitweb: http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/generic-dma-noncoherent.2 Changes since v1: - dropped the already merged generic, arc and c6x patches (with the map_single offset fix from Alexey Brodkin) - split various changes into smaller patches - dropped the arm-nommu changes for now - fixed a typo Changes since RFC: - fix a typo accidentally disabling the device to cpu transfer sync - fixed a few compile failures