[PATCH 1/7] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code

[PATCH 1/7] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The ddi code no longer uses intel_ddi_get_crtc_new_encoder(). Move it
elsewhere where we have some users left.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 29 -----------------------------
 drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h     |  2 --
 3 files changed, 30 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1665bc588241..3b8f12883ca7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1243,35 +1243,6 @@ intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
 	return ret;
 }
 
-/* Finds the only possible encoder associated with the given CRTC. */
-struct intel_encoder *
-intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	struct intel_encoder *ret = NULL;
-	struct drm_atomic_state *state;
-	struct drm_connector *connector;
-	struct drm_connector_state *connector_state;
-	int num_encoders = 0;
-	int i;
-
-	state = crtc_state->base.state;
-
-	for_each_new_connector_in_state(state, connector, connector_state, i) {
-		if (connector_state->crtc != crtc_state->base.crtc)
-			continue;
-
-		ret = to_intel_encoder(connector_state->best_encoder);
-		num_encoders++;
-	}
-
-	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
-	     pipe_name(crtc->pipe));
-
-	BUG_ON(ret == NULL);
-	return ret;
-}
-
 #define LC_FREQ 2700
 
 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c9ec88acad9c..bc13d3ec779b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4589,6 +4589,35 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
 	}
 }
 
+/*
+ * Finds the encoder associated with the given CRTC. This can only be
+ * used when we know that the CRTC isn't feeding multiple encoders!
+ */
+static struct intel_encoder *
+intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	const struct drm_atomic_state *state = crtc_state->base.state;
+	const struct drm_connector_state *connector_state;
+	const struct drm_connector *connector;
+	struct intel_encoder *encoder = NULL;
+	int num_encoders = 0;
+	int i;
+
+	for_each_new_connector_in_state(state, connector, connector_state, i) {
+		if (connector_state->crtc != &crtc->base)
+			continue;
+
+		encoder = to_intel_encoder(connector_state->best_encoder);
+		num_encoders++;
+	}
+
+	WARN(num_encoders != 1, "%d encoders for pipe %c\n",
+	     num_encoders, pipe_name(crtc->pipe));
+
+	return encoder;
+}
+
 /* Return which DP Port should be selected for Transcoder DP control */
 static enum port
 intel_trans_dp_port_sel(struct intel_crtc *crtc)
@@ -9102,7 +9131,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 {
 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
 		struct intel_encoder *encoder =
-			intel_ddi_get_crtc_new_encoder(crtc_state);
+			intel_get_crtc_new_encoder(crtc_state);
 
 		if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
 			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 22af249393a4..a827a2245c18 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1395,8 +1395,6 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 				       enum transcoder cpu_transcoder);
 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
-struct intel_encoder *
-intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
-- 
2.16.1

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[PATCH v2 2/7] drm/i915: Parametrize TRANS_DP_PORT_SEL

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Parametrize the TRANS_DP_PORT_SEL macros.

v2: WARN for bogus ports (Jani)
    Order the defines mask,value (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  8 +++-----
 drivers/gpu/drm/i915/intel_display.c | 24 ++++++++----------------
 2 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb79272..5a103496423c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7887,11 +7887,9 @@ enum {
 #define _TRANS_DP_CTL_C		0xe2300
 #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
 #define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
-#define  TRANS_DP_PORT_SEL_B	(0<<29)
-#define  TRANS_DP_PORT_SEL_C	(1<<29)
-#define  TRANS_DP_PORT_SEL_D	(2<<29)
-#define  TRANS_DP_PORT_SEL_NONE	(3<<29)
-#define  TRANS_DP_PORT_SEL_MASK	(3<<29)
+#define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
+#define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
+#define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
 #define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
 #define  TRANS_DP_AUDIO_ONLY	(1<<26)
 #define  TRANS_DP_ENH_FRAMING	(1<<18)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bc13d3ec779b..a85f77aebd12 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1360,9 +1360,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 {
 	enum pipe port_pipe;
 
-	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
-	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
-	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
+	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL(PORT_B));
+	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL(PORT_C));
+	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL(PORT_D));
 
 	I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
 			port_pipe == pipe,
@@ -4701,6 +4701,8 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
 			&crtc_state->base.adjusted_mode;
 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
 		i915_reg_t reg = TRANS_DP_CTL(pipe);
+		enum port port;
+
 		temp = I915_READ(reg);
 		temp &= ~(TRANS_DP_PORT_SEL_MASK |
 			  TRANS_DP_SYNC_MASK |
@@ -4713,19 +4715,9 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
-		switch (intel_trans_dp_port_sel(crtc)) {
-		case PORT_B:
-			temp |= TRANS_DP_PORT_SEL_B;
-			break;
-		case PORT_C:
-			temp |= TRANS_DP_PORT_SEL_C;
-			break;
-		case PORT_D:
-			temp |= TRANS_DP_PORT_SEL_D;
-			break;
-		default:
-			BUG();
-		}
+		port = intel_trans_dp_port_sel(crtc);
+		WARN_ON(port < PORT_B || port > PORT_D);
+		temp |= TRANS_DP_PORT_SEL(port);
 
 		I915_WRITE(reg, temp);
 	}
-- 
2.16.1

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[PATCH 3/7] drm/i915: Nuke intel_trans_dp_port_sel()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

for_each_encoder_on_crtc() is legacy and shouldn't be used by atomic
drivers. Let's throw out intel_trans_dp_port_sel() and replace it
with intel_get_crtc_new_encoder() which looks the atomic state instead.

Since we now have to call intel_get_crtc_new_encoder() during the commit
phase we'll need to plumb in the top level atomic state. The
crtc_state->state pointers are no longer valid at that point.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 39 +++++++++++++-----------------------
 1 file changed, 14 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a85f77aebd12..d36dea568b82 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4594,17 +4594,17 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
  * used when we know that the CRTC isn't feeding multiple encoders!
  */
 static struct intel_encoder *
-intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
+intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
+			   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_atomic_state *state = crtc_state->base.state;
 	const struct drm_connector_state *connector_state;
 	const struct drm_connector *connector;
 	struct intel_encoder *encoder = NULL;
 	int num_encoders = 0;
 	int i;
 
-	for_each_new_connector_in_state(state, connector, connector_state, i) {
+	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 		if (connector_state->crtc != &crtc->base)
 			continue;
 
@@ -4618,22 +4618,6 @@ intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
 	return encoder;
 }
 
-/* Return which DP Port should be selected for Transcoder DP control */
-static enum port
-intel_trans_dp_port_sel(struct intel_crtc *crtc)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct intel_encoder *encoder;
-
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
-		if (encoder->type == INTEL_OUTPUT_DP ||
-		    encoder->type == INTEL_OUTPUT_EDP)
-			return encoder->port;
-	}
-
-	return -1;
-}
-
 /*
  * Enable PCH resources required for PCH ports:
  *   - PCH PLLs
@@ -4642,7 +4626,8 @@ intel_trans_dp_port_sel(struct intel_crtc *crtc)
  *   - DP transcoding bits
  *   - transcoder
  */
-static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
+static void ironlake_pch_enable(const struct intel_atomic_state *state,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_device *dev = crtc->base.dev;
@@ -4715,7 +4700,7 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
-		port = intel_trans_dp_port_sel(crtc);
+		port = intel_get_crtc_new_encoder(state, crtc_state)->port;
 		WARN_ON(port < PORT_B || port > PORT_D);
 		temp |= TRANS_DP_PORT_SEL(port);
 
@@ -4725,7 +4710,8 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
 	ironlake_enable_pch_transcoder(dev_priv, pipe);
 }
 
-static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
+static void lpt_pch_enable(const struct intel_atomic_state *state,
+			   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -5528,7 +5514,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
 	intel_enable_pipe(pipe_config);
 
 	if (intel_crtc->config->has_pch_encoder)
-		ironlake_pch_enable(pipe_config);
+		ironlake_pch_enable(old_intel_state, pipe_config);
 
 	assert_vblank_disabled(crtc);
 	drm_crtc_vblank_on(crtc);
@@ -5667,7 +5653,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 		intel_enable_pipe(pipe_config);
 
 	if (intel_crtc->config->has_pch_encoder)
-		lpt_pch_enable(pipe_config);
+		lpt_pch_enable(old_intel_state, pipe_config);
 
 	if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
 		intel_ddi_set_vc_payload_alloc(pipe_config, true);
@@ -9121,9 +9107,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state)
 {
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(crtc_state->base.state);
+
 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
 		struct intel_encoder *encoder =
-			intel_get_crtc_new_encoder(crtc_state);
+			intel_get_crtc_new_encoder(state, crtc_state);
 
 		if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
 			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
-- 
2.16.1

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[PATCH v3 4/7] drm/i915: Clean up DP pipe select bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Clean up the DP pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state(),
the port state asserts, and the VLV power sequencer code.

v2: Return PIPE_A for cpt/ppt when the port isn't selected by
    any transcoder. Returning INVALID_PIPE explodes *somewhere*
    on some machines (can't immediately see where though). This
    now matches the old behaviour.
v3: Order the defines shift,mask,value (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  24 +++-----
 drivers/gpu/drm/i915/intel_display.c |  48 +++++----------
 drivers/gpu/drm/i915/intel_dp.c      | 113 ++++++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_drv.h     |   3 +
 4 files changed, 92 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a103496423c..b888da96caf7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5182,10 +5182,15 @@ enum {
 #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
 
 #define   DP_PORT_EN			(1 << 31)
-#define   DP_PIPEB_SELECT		(1 << 30)
-#define   DP_PIPE_MASK			(1 << 30)
-#define   DP_PIPE_SELECT_CHV(pipe)	((pipe) << 16)
-#define   DP_PIPE_MASK_CHV		(3 << 16)
+#define   DP_PIPE_SEL_SHIFT		30
+#define   DP_PIPE_SEL_MASK		(1 << 30)
+#define   DP_PIPE_SEL(pipe)		((pipe) << 30)
+#define   DP_PIPE_SEL_SHIFT_IVB		29
+#define   DP_PIPE_SEL_MASK_IVB		(3 << 29)
+#define   DP_PIPE_SEL_IVB(pipe)		((pipe) << 29)
+#define   DP_PIPE_SEL_SHIFT_CHV		16
+#define   DP_PIPE_SEL_MASK_CHV		(3 << 16)
+#define   DP_PIPE_SEL_CHV(pipe)		((pipe) << 16)
 
 /* Link training mode - select a suitable mode for each stage */
 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
@@ -7872,16 +7877,6 @@ enum {
 #define PCH_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
-#define  PORT_TRANS_A_SEL_CPT	0
-#define  PORT_TRANS_B_SEL_CPT	(1<<29)
-#define  PORT_TRANS_C_SEL_CPT	(2<<29)
-#define  PORT_TRANS_SEL_MASK	(3<<29)
-#define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
-#define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
-#define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
-#define  SDVO_PORT_TO_PIPE_CHV(val)	(((val) & (3<<24)) >> 24)
-#define  DP_PORT_TO_PIPE_CHV(val)	(((val) & (3<<16)) >> 16)
-
 #define _TRANS_DP_CTL_A		0xe0300
 #define _TRANS_DP_CTL_B		0xe1300
 #define _TRANS_DP_CTL_C		0xe2300
@@ -7890,7 +7885,6 @@ enum {
 #define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
 #define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
 #define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
-#define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
 #define  TRANS_DP_AUDIO_ONLY	(1<<26)
 #define  TRANS_DP_ENH_FRAMING	(1<<18)
 #define  TRANS_DP_8BPC		(0<<9)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d36dea568b82..d397febb5a7f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1303,38 +1303,22 @@ void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 	     pipe_name(pipe));
 }
 
-static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
-			    enum pipe pipe, u32 port_sel, u32 val)
-{
-	if ((val & DP_PORT_EN) == 0)
-		return false;
-
-	if (HAS_PCH_CPT(dev_priv)) {
-		u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
-		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
-			return false;
-	} else if (IS_CHERRYVIEW(dev_priv)) {
-		if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
-			return false;
-	} else {
-		if ((val & DP_PIPE_MASK) != (pipe << 30))
-			return false;
-	}
-	return true;
-}
-
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
-				   enum pipe pipe, i915_reg_t reg,
-				   u32 port_sel)
+				   enum pipe pipe, enum port port,
+				   i915_reg_t dp_reg)
 {
-	u32 val = I915_READ(reg);
-	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
-	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
-	     i915_mmio_reg_offset(reg), pipe_name(pipe));
+	enum pipe port_pipe;
+	bool state;
 
-	I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
-	     && (val & DP_PIPEB_SELECT),
-	     "IBX PCH dp port still using transcoder B\n");
+	state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
+
+	I915_STATE_WARN(state && port_pipe == pipe,
+			"PCH DP %c enabled on transcoder %c, should be disabled\n",
+			port_name(port), pipe_name(pipe));
+
+	I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
+			"IBX PCH DP %c still using transcoder B\n",
+			port_name(port));
 }
 
 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
@@ -1360,9 +1344,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 {
 	enum pipe port_pipe;
 
-	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL(PORT_B));
-	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL(PORT_C));
-	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL(PORT_D));
+	assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
+	assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
+	assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
 
 	I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
 			port_pipe == pipe,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 102070940095..aab48283f155 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -529,9 +529,9 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 	DP |= DP_LINK_TRAIN_PAT_1;
 
 	if (IS_CHERRYVIEW(dev_priv))
-		DP |= DP_PIPE_SELECT_CHV(pipe);
-	else if (pipe == PIPE_B)
-		DP |= DP_PIPEB_SELECT;
+		DP |= DP_PIPE_SEL_CHV(pipe);
+	else
+		DP |= DP_PIPE_SEL(pipe);
 
 	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 
@@ -1999,7 +1999,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 			intel_dp->DP |= DP_ENHANCED_FRAMING;
 
-		intel_dp->DP |= crtc->pipe << 29;
+		intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
 	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
 		u32 trans_dp;
 
@@ -2025,9 +2025,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 			intel_dp->DP |= DP_ENHANCED_FRAMING;
 
 		if (IS_CHERRYVIEW(dev_priv))
-			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
-		else if (crtc->pipe == PIPE_B)
-			intel_dp->DP |= DP_PIPEB_SELECT;
+			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
+		else
+			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
 	}
 }
 
@@ -2649,52 +2649,66 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
 }
 
+static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
+				 enum port port, enum pipe *pipe)
+{
+	enum pipe p;
+
+	for_each_pipe(dev_priv, p) {
+		u32 val = I915_READ(TRANS_DP_CTL(p));
+
+		if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
+			*pipe = p;
+			return true;
+		}
+	}
+
+	DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
+
+	/* must initialize pipe to something for the asserts */
+	*pipe = PIPE_A;
+
+	return false;
+}
+
+bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
+			   i915_reg_t dp_reg, enum port port,
+			   enum pipe *pipe)
+{
+	bool ret;
+	u32 val;
+
+	val = I915_READ(dp_reg);
+
+	ret = val & DP_PORT_EN;
+
+	/* asserts want to know the pipe even if the port is disabled */
+	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
+		*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
+	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
+		ret &= cpt_dp_port_selected(dev_priv, port, pipe);
+	else if (IS_CHERRYVIEW(dev_priv))
+		*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
+	else
+		*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
+
+	return ret;
+}
+
 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 				  enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	enum port port = encoder->port;
-	u32 tmp;
 	bool ret;
 
 	if (!intel_display_power_get_if_enabled(dev_priv,
 						encoder->power_domain))
 		return false;
 
-	ret = false;
+	ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
+				    encoder->port, pipe);
 
-	tmp = I915_READ(intel_dp->output_reg);
-
-	if (!(tmp & DP_PORT_EN))
-		goto out;
-
-	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
-		*pipe = PORT_TO_PIPE_CPT(tmp);
-	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
-		enum pipe p;
-
-		for_each_pipe(dev_priv, p) {
-			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
-			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
-				*pipe = p;
-				ret = true;
-
-				goto out;
-			}
-		}
-
-		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
-			      i915_mmio_reg_offset(intel_dp->output_reg));
-	} else if (IS_CHERRYVIEW(dev_priv)) {
-		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
-	} else {
-		*pipe = PORT_TO_PIPE(tmp);
-	}
-
-	ret = true;
-
-out:
 	intel_display_power_put(dev_priv, encoder->power_domain);
 
 	return ret;
@@ -3684,8 +3698,9 @@ intel_dp_link_down(struct intel_encoder *encoder,
 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 
 		/* always enable with pattern 1 (as per spec) */
-		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
-		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
+		DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
+		DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
+			DP_LINK_TRAIN_PAT_1;
 		I915_WRITE(intel_dp->output_reg, DP);
 		POSTING_READ(intel_dp->output_reg);
 
@@ -5320,14 +5335,14 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	enum pipe pipe;
 
-	if ((intel_dp->DP & DP_PORT_EN) == 0)
-		return INVALID_PIPE;
+	if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
+				  encoder->port, &pipe))
+		return pipe;
 
-	if (IS_CHERRYVIEW(dev_priv))
-		return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
-	else
-		return PORT_TO_PIPE(intel_dp->DP);
+	return INVALID_PIPE;
 }
 
 void intel_dp_encoder_reset(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a827a2245c18..dc7f81e1e20a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1647,6 +1647,9 @@ void intel_csr_ucode_suspend(struct drm_i915_private *);
 void intel_csr_ucode_resume(struct drm_i915_private *);
 
 /* intel_dp.c */
+bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
+			   i915_reg_t dp_reg, enum port port,
+			   enum pipe *pipe);
 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
 		   enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
-- 
2.16.1

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[PATCH 5/7] drm/i915: Allow eDP on port C in theory

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The power sequencer has bits to allow DP C to be used for eDP.
Currently we assume this will never happen, but I guess it could
theoretically be a thing. Make the code do the right thing in that
case, and toss in a MISSING_CASE() for any other port.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aab48283f155..fdec8f18a52a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5737,10 +5737,20 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		port_sel = PANEL_PORT_SELECT_VLV(port);
 	} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
-		if (port == PORT_A)
+		switch (port) {
+		case PORT_A:
 			port_sel = PANEL_PORT_SELECT_DPA;
-		else
+			break;
+		case PORT_C:
+			port_sel = PANEL_PORT_SELECT_DPC;
+			break;
+		case PORT_D:
 			port_sel = PANEL_PORT_SELECT_DPD;
+			break;
+		default:
+			MISSING_CASE(port);
+			break;
+		}
 	}
 
 	pp_on |= port_sel;
-- 
2.16.1

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[PATCH 6/7] drm/i915: Implement the missing bits of assert_panel_unlocked()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the missing eDP port handling into assert_panel_unlocked(). We now
have intel_dp_port_enabled() which makes this trivial.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d397febb5a7f..a7702a72cd69 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1214,9 +1214,23 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
 		pp_reg = PP_CONTROL(0);
 		port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
 
-		if (port_sel == PANEL_PORT_SELECT_LVDS)
+		switch (port_sel) {
+		case PANEL_PORT_SELECT_LVDS:
 			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
-		/* XXX: else fix for eDP */
+			break;
+		case PANEL_PORT_SELECT_DPA:
+			intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
+			break;
+		case PANEL_PORT_SELECT_DPC:
+			intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
+			break;
+		case PANEL_PORT_SELECT_DPD:
+			intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
+			break;
+		default:
+			MISSING_CASE(port_sel);
+			break;
+		}
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		/* presumably write lock depends on pipe, not port select */
 		pp_reg = PP_CONTROL(pipe);
-- 
2.16.1

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[PATCH 7/7] drm/i915: WARN if power sequencer is not connected to the LVDS port on pre-ilk

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We don't support using the power sequencer with other ports besides LVDS
on pre-ilk platforms. WARN if someone has mistakenly connected the power
sequencer to the wrong port.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a7702a72cd69..4773a4f52bfe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1236,7 +1236,12 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
 		pp_reg = PP_CONTROL(pipe);
 		panel_pipe = pipe;
 	} else {
+		u32 port_sel;
+
 		pp_reg = PP_CONTROL(0);
+		port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
+
+		WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
 		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
 	}
 
-- 
2.16.1

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✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code
URL   : https://patchwork.freedesktop.org/series/43426/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9054 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9054 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9054, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43426/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9054:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_9054 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-4200u:       PASS -> DMESG-FAIL (fdo#102614, fdo#106103)
      fi-hsw-peppy:       PASS -> DMESG-FAIL (fdo#102614, fdo#106103)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-cnl-y3:          PASS -> DMESG-WARN (fdo#104951)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
      fi-hsw-4200u:       FAIL (fdo#103481) -> PASS

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 39) ==

  Missing    (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4209 -> Patchwork_9054

  CI_DRM_4209: eecb2c1e793ed98c39876c92fc64cd18a7fe6412 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9054: 577b8c947eaa70bc4d14a9ddb9121b517c273f05 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit


== Linux commits ==

577b8c947eaa drm/i915: WARN if power sequencer is not connected to the LVDS port on pre-ilk
161ccec367de drm/i915: Implement the missing bits of assert_panel_unlocked()
df1eacf99a00 drm/i915: Allow eDP on port C in theory
8ed336daa896 drm/i915: Clean up DP pipe select bits
73b6d313c32a drm/i915: Nuke intel_trans_dp_port_sel()
f9409bb16382 drm/i915: Parametrize TRANS_DP_PORT_SEL
2271be2c9677 drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9054/issues.html
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✓ Fi.CI.IGT: success for series starting with [1/7] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code
URL   : https://patchwork.freedesktop.org/series/43426/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4209_full -> Patchwork_9054_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9054_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9054_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43426/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9054_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd2:
      shard-kbl:          SKIP -> PASS +2

    igt@gem_mocs_settings@mocs-rc6-dirty-render:
      shard-kbl:          PASS -> SKIP +1

    igt@kms_plane_lowres@pipe-c-tiling-x:
      shard-apl:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_9054_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_render_copy_redux@interruptible:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665)

    igt@kms_flip@plain-flip-ts-check:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_flip_tiling@flip-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#103822, fdo#104724)

    igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack:
      shard-hsw:          PASS -> DMESG-WARN (fdo#102614)

    
    ==== Possible fixes ====

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
      shard-glk:          FAIL (fdo#105703) -> PASS

    igt@kms_flip_tiling@flip-to-y-tiled:
      shard-glk:          FAIL (fdo#104724) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
      shard-apl:          DMESG-FAIL (fdo#103558, fdo#105602) -> PASS

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt:
      shard-glk:          FAIL (fdo#103167, fdo#104724) -> PASS +1

    igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
      shard-apl:          DMESG-WARN (fdo#103558, fdo#105602) -> PASS +9

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4209 -> Patchwork_9054

  CI_DRM_4209: eecb2c1e793ed98c39876c92fc64cd18a7fe6412 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9054: 577b8c947eaa70bc4d14a9ddb9121b517c273f05 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9054/shards.html
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Re: [PATCH 1/7] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code

[Jani Nikula]

On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The ddi code no longer uses intel_ddi_get_crtc_new_encoder(). Move it
> elsewhere where we have some users left.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yup.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 29 -----------------------------
>  drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_drv.h     |  2 --
>  3 files changed, 30 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 1665bc588241..3b8f12883ca7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1243,35 +1243,6 @@ intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
>  	return ret;
>  }
>  
> -/* Finds the only possible encoder associated with the given CRTC. */
> -struct intel_encoder *
> -intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	struct intel_encoder *ret = NULL;
> -	struct drm_atomic_state *state;
> -	struct drm_connector *connector;
> -	struct drm_connector_state *connector_state;
> -	int num_encoders = 0;
> -	int i;
> -
> -	state = crtc_state->base.state;
> -
> -	for_each_new_connector_in_state(state, connector, connector_state, i) {
> -		if (connector_state->crtc != crtc_state->base.crtc)
> -			continue;
> -
> -		ret = to_intel_encoder(connector_state->best_encoder);
> -		num_encoders++;
> -	}
> -
> -	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
> -	     pipe_name(crtc->pipe));
> -
> -	BUG_ON(ret == NULL);
> -	return ret;
> -}
> -
>  #define LC_FREQ 2700
>  
>  static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c9ec88acad9c..bc13d3ec779b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4589,6 +4589,35 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
>  	}
>  }
>  
> +/*
> + * Finds the encoder associated with the given CRTC. This can only be
> + * used when we know that the CRTC isn't feeding multiple encoders!
> + */
> +static struct intel_encoder *
> +intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	const struct drm_atomic_state *state = crtc_state->base.state;
> +	const struct drm_connector_state *connector_state;
> +	const struct drm_connector *connector;
> +	struct intel_encoder *encoder = NULL;
> +	int num_encoders = 0;
> +	int i;
> +
> +	for_each_new_connector_in_state(state, connector, connector_state, i) {
> +		if (connector_state->crtc != &crtc->base)
> +			continue;
> +
> +		encoder = to_intel_encoder(connector_state->best_encoder);
> +		num_encoders++;
> +	}
> +
> +	WARN(num_encoders != 1, "%d encoders for pipe %c\n",
> +	     num_encoders, pipe_name(crtc->pipe));
> +
> +	return encoder;
> +}
> +
>  /* Return which DP Port should be selected for Transcoder DP control */
>  static enum port
>  intel_trans_dp_port_sel(struct intel_crtc *crtc)
> @@ -9102,7 +9131,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  {
>  	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
>  		struct intel_encoder *encoder =
> -			intel_ddi_get_crtc_new_encoder(crtc_state);
> +			intel_get_crtc_new_encoder(crtc_state);
>  
>  		if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
>  			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 22af249393a4..a827a2245c18 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1395,8 +1395,6 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
>  				       enum transcoder cpu_transcoder);
>  void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
>  void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
> -struct intel_encoder *
> -intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
>  void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
>  void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
>  bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 2/7] drm/i915: Parametrize TRANS_DP_PORT_SEL

[Jani Nikula]

On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Parametrize the TRANS_DP_PORT_SEL macros.
>
> v2: WARN for bogus ports (Jani)
>     Order the defines mask,value (Jani)
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yup.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  8 +++-----
>  drivers/gpu/drm/i915/intel_display.c | 24 ++++++++----------------
>  2 files changed, 11 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 196a0eb79272..5a103496423c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7887,11 +7887,9 @@ enum {
>  #define _TRANS_DP_CTL_C		0xe2300
>  #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
>  #define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
> -#define  TRANS_DP_PORT_SEL_B	(0<<29)
> -#define  TRANS_DP_PORT_SEL_C	(1<<29)
> -#define  TRANS_DP_PORT_SEL_D	(2<<29)
> -#define  TRANS_DP_PORT_SEL_NONE	(3<<29)
> -#define  TRANS_DP_PORT_SEL_MASK	(3<<29)
> +#define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
> +#define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
> +#define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
>  #define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
>  #define  TRANS_DP_AUDIO_ONLY	(1<<26)
>  #define  TRANS_DP_ENH_FRAMING	(1<<18)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bc13d3ec779b..a85f77aebd12 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1360,9 +1360,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  {
>  	enum pipe port_pipe;
>  
> -	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
> -	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
> -	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
> +	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL(PORT_B));
> +	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL(PORT_C));
> +	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL(PORT_D));
>  
>  	I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
>  			port_pipe == pipe,
> @@ -4701,6 +4701,8 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
>  			&crtc_state->base.adjusted_mode;
>  		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
>  		i915_reg_t reg = TRANS_DP_CTL(pipe);
> +		enum port port;
> +
>  		temp = I915_READ(reg);
>  		temp &= ~(TRANS_DP_PORT_SEL_MASK |
>  			  TRANS_DP_SYNC_MASK |
> @@ -4713,19 +4715,9 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
>  			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
>  
> -		switch (intel_trans_dp_port_sel(crtc)) {
> -		case PORT_B:
> -			temp |= TRANS_DP_PORT_SEL_B;
> -			break;
> -		case PORT_C:
> -			temp |= TRANS_DP_PORT_SEL_C;
> -			break;
> -		case PORT_D:
> -			temp |= TRANS_DP_PORT_SEL_D;
> -			break;
> -		default:
> -			BUG();
> -		}
> +		port = intel_trans_dp_port_sel(crtc);
> +		WARN_ON(port < PORT_B || port > PORT_D);
> +		temp |= TRANS_DP_PORT_SEL(port);
>  
>  		I915_WRITE(reg, temp);
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/7] drm/i915: Nuke intel_trans_dp_port_sel()

[Jani Nikula]

On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> for_each_encoder_on_crtc() is legacy and shouldn't be used by atomic
> drivers. Let's throw out intel_trans_dp_port_sel() and replace it
> with intel_get_crtc_new_encoder() which looks the atomic state instead.
>
> Since we now have to call intel_get_crtc_new_encoder() during the commit
> phase we'll need to plumb in the top level atomic state. The
> crtc_state->state pointers are no longer valid at that point.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 39 +++++++++++++-----------------------
>  1 file changed, 14 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a85f77aebd12..d36dea568b82 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4594,17 +4594,17 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
>   * used when we know that the CRTC isn't feeding multiple encoders!
>   */
>  static struct intel_encoder *
> -intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
> +intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
> +			   const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_atomic_state *state = crtc_state->base.state;
>  	const struct drm_connector_state *connector_state;
>  	const struct drm_connector *connector;
>  	struct intel_encoder *encoder = NULL;
>  	int num_encoders = 0;
>  	int i;
>  
> -	for_each_new_connector_in_state(state, connector, connector_state, i) {
> +	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
>  		if (connector_state->crtc != &crtc->base)
>  			continue;
>  
> @@ -4618,22 +4618,6 @@ intel_get_crtc_new_encoder(const struct intel_crtc_state *crtc_state)
>  	return encoder;
>  }
>  
> -/* Return which DP Port should be selected for Transcoder DP control */
> -static enum port
> -intel_trans_dp_port_sel(struct intel_crtc *crtc)
> -{
> -	struct drm_device *dev = crtc->base.dev;
> -	struct intel_encoder *encoder;
> -
> -	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
> -		if (encoder->type == INTEL_OUTPUT_DP ||
> -		    encoder->type == INTEL_OUTPUT_EDP)
> -			return encoder->port;
> -	}
> -
> -	return -1;
> -}

Glad to see this go, fingers crossed the sanity checks in
intel_get_crtc_new_encoder() and ironlake_pch_enable() will give enough
debug details in case this goes boom. ;)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> -
>  /*
>   * Enable PCH resources required for PCH ports:
>   *   - PCH PLLs
> @@ -4642,7 +4626,8 @@ intel_trans_dp_port_sel(struct intel_crtc *crtc)
>   *   - DP transcoding bits
>   *   - transcoder
>   */
> -static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
> +static void ironlake_pch_enable(const struct intel_atomic_state *state,
> +				const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_device *dev = crtc->base.dev;
> @@ -4715,7 +4700,7 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
>  			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
>  
> -		port = intel_trans_dp_port_sel(crtc);
> +		port = intel_get_crtc_new_encoder(state, crtc_state)->port;
>  		WARN_ON(port < PORT_B || port > PORT_D);
>  		temp |= TRANS_DP_PORT_SEL(port);
>  
> @@ -4725,7 +4710,8 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
>  	ironlake_enable_pch_transcoder(dev_priv, pipe);
>  }
>  
> -static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
> +static void lpt_pch_enable(const struct intel_atomic_state *state,
> +			   const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -5528,7 +5514,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>  	intel_enable_pipe(pipe_config);
>  
>  	if (intel_crtc->config->has_pch_encoder)
> -		ironlake_pch_enable(pipe_config);
> +		ironlake_pch_enable(old_intel_state, pipe_config);
>  
>  	assert_vblank_disabled(crtc);
>  	drm_crtc_vblank_on(crtc);
> @@ -5667,7 +5653,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  		intel_enable_pipe(pipe_config);
>  
>  	if (intel_crtc->config->has_pch_encoder)
> -		lpt_pch_enable(pipe_config);
> +		lpt_pch_enable(old_intel_state, pipe_config);
>  
>  	if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
>  		intel_ddi_set_vc_payload_alloc(pipe_config, true);
> @@ -9121,9 +9107,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  				      struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_atomic_state *state =
> +		to_intel_atomic_state(crtc_state->base.state);
> +
>  	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
>  		struct intel_encoder *encoder =
> -			intel_get_crtc_new_encoder(crtc_state);
> +			intel_get_crtc_new_encoder(state, crtc_state);
>  
>  		if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
>  			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
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Re: [PATCH v3 4/7] drm/i915: Clean up DP pipe select bits

[Jani Nikula]

On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Clean up the DP pipe select bits. To make the whole situation a bit
> less ugly we'll start to share the same code between .get_hw_state(),
> the port state asserts, and the VLV power sequencer code.
>
> v2: Return PIPE_A for cpt/ppt when the port isn't selected by
>     any transcoder. Returning INVALID_PIPE explodes *somewhere*
>     on some machines (can't immediately see where though). This
>     now matches the old behaviour.
> v3: Order the defines shift,mask,value (Jani)
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I could've bikeshedded about some naming here, but I don't want to read
this particular patch again, so

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  24 +++-----
>  drivers/gpu/drm/i915/intel_display.c |  48 +++++----------
>  drivers/gpu/drm/i915/intel_dp.c      | 113 ++++++++++++++++++++---------------
>  drivers/gpu/drm/i915/intel_drv.h     |   3 +
>  4 files changed, 92 insertions(+), 96 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5a103496423c..b888da96caf7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5182,10 +5182,15 @@ enum {
>  #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
>  
>  #define   DP_PORT_EN			(1 << 31)
> -#define   DP_PIPEB_SELECT		(1 << 30)
> -#define   DP_PIPE_MASK			(1 << 30)
> -#define   DP_PIPE_SELECT_CHV(pipe)	((pipe) << 16)
> -#define   DP_PIPE_MASK_CHV		(3 << 16)
> +#define   DP_PIPE_SEL_SHIFT		30
> +#define   DP_PIPE_SEL_MASK		(1 << 30)
> +#define   DP_PIPE_SEL(pipe)		((pipe) << 30)
> +#define   DP_PIPE_SEL_SHIFT_IVB		29
> +#define   DP_PIPE_SEL_MASK_IVB		(3 << 29)
> +#define   DP_PIPE_SEL_IVB(pipe)		((pipe) << 29)
> +#define   DP_PIPE_SEL_SHIFT_CHV		16
> +#define   DP_PIPE_SEL_MASK_CHV		(3 << 16)
> +#define   DP_PIPE_SEL_CHV(pipe)		((pipe) << 16)
>  
>  /* Link training mode - select a suitable mode for each stage */
>  #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
> @@ -7872,16 +7877,6 @@ enum {
>  #define PCH_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>  
>  /* CPT */
> -#define  PORT_TRANS_A_SEL_CPT	0
> -#define  PORT_TRANS_B_SEL_CPT	(1<<29)
> -#define  PORT_TRANS_C_SEL_CPT	(2<<29)
> -#define  PORT_TRANS_SEL_MASK	(3<<29)
> -#define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
> -#define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
> -#define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
> -#define  SDVO_PORT_TO_PIPE_CHV(val)	(((val) & (3<<24)) >> 24)
> -#define  DP_PORT_TO_PIPE_CHV(val)	(((val) & (3<<16)) >> 16)
> -
>  #define _TRANS_DP_CTL_A		0xe0300
>  #define _TRANS_DP_CTL_B		0xe1300
>  #define _TRANS_DP_CTL_C		0xe2300
> @@ -7890,7 +7885,6 @@ enum {
>  #define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
>  #define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
>  #define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
> -#define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
>  #define  TRANS_DP_AUDIO_ONLY	(1<<26)
>  #define  TRANS_DP_ENH_FRAMING	(1<<18)
>  #define  TRANS_DP_8BPC		(0<<9)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d36dea568b82..d397febb5a7f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1303,38 +1303,22 @@ void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
>  	     pipe_name(pipe));
>  }
>  
> -static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
> -			    enum pipe pipe, u32 port_sel, u32 val)
> -{
> -	if ((val & DP_PORT_EN) == 0)
> -		return false;
> -
> -	if (HAS_PCH_CPT(dev_priv)) {
> -		u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
> -		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
> -			return false;
> -	} else if (IS_CHERRYVIEW(dev_priv)) {
> -		if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
> -			return false;
> -	} else {
> -		if ((val & DP_PIPE_MASK) != (pipe << 30))
> -			return false;
> -	}
> -	return true;
> -}
> -
>  static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
> -				   enum pipe pipe, i915_reg_t reg,
> -				   u32 port_sel)
> +				   enum pipe pipe, enum port port,
> +				   i915_reg_t dp_reg)
>  {
> -	u32 val = I915_READ(reg);
> -	I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
> -	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
> -	     i915_mmio_reg_offset(reg), pipe_name(pipe));
> +	enum pipe port_pipe;
> +	bool state;
>  
> -	I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
> -	     && (val & DP_PIPEB_SELECT),
> -	     "IBX PCH dp port still using transcoder B\n");
> +	state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
> +
> +	I915_STATE_WARN(state && port_pipe == pipe,
> +			"PCH DP %c enabled on transcoder %c, should be disabled\n",
> +			port_name(port), pipe_name(pipe));
> +
> +	I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
> +			"IBX PCH DP %c still using transcoder B\n",
> +			port_name(port));
>  }
>  
>  static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
> @@ -1360,9 +1344,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  {
>  	enum pipe port_pipe;
>  
> -	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL(PORT_B));
> -	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL(PORT_C));
> -	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL(PORT_D));
> +	assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
> +	assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
> +	assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
>  
>  	I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
>  			port_pipe == pipe,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 102070940095..aab48283f155 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -529,9 +529,9 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
>  	DP |= DP_LINK_TRAIN_PAT_1;
>  
>  	if (IS_CHERRYVIEW(dev_priv))
> -		DP |= DP_PIPE_SELECT_CHV(pipe);
> -	else if (pipe == PIPE_B)
> -		DP |= DP_PIPEB_SELECT;
> +		DP |= DP_PIPE_SEL_CHV(pipe);
> +	else
> +		DP |= DP_PIPE_SEL(pipe);
>  
>  	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
>  
> @@ -1999,7 +1999,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>  		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>  			intel_dp->DP |= DP_ENHANCED_FRAMING;
>  
> -		intel_dp->DP |= crtc->pipe << 29;
> +		intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
>  	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
>  		u32 trans_dp;
>  
> @@ -2025,9 +2025,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>  			intel_dp->DP |= DP_ENHANCED_FRAMING;
>  
>  		if (IS_CHERRYVIEW(dev_priv))
> -			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
> -		else if (crtc->pipe == PIPE_B)
> -			intel_dp->DP |= DP_PIPEB_SELECT;
> +			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
> +		else
> +			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
>  	}
>  }
>  
> @@ -2649,52 +2649,66 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
>  			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
>  }
>  
> +static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
> +				 enum port port, enum pipe *pipe)
> +{
> +	enum pipe p;
> +
> +	for_each_pipe(dev_priv, p) {
> +		u32 val = I915_READ(TRANS_DP_CTL(p));
> +
> +		if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
> +			*pipe = p;
> +			return true;
> +		}
> +	}
> +
> +	DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
> +
> +	/* must initialize pipe to something for the asserts */
> +	*pipe = PIPE_A;
> +
> +	return false;
> +}
> +
> +bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
> +			   i915_reg_t dp_reg, enum port port,
> +			   enum pipe *pipe)
> +{
> +	bool ret;
> +	u32 val;
> +
> +	val = I915_READ(dp_reg);
> +
> +	ret = val & DP_PORT_EN;
> +
> +	/* asserts want to know the pipe even if the port is disabled */
> +	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
> +		*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
> +	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
> +		ret &= cpt_dp_port_selected(dev_priv, port, pipe);
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
> +	else
> +		*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
> +
> +	return ret;
> +}
> +
>  static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  				  enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> -	enum port port = encoder->port;
> -	u32 tmp;
>  	bool ret;
>  
>  	if (!intel_display_power_get_if_enabled(dev_priv,
>  						encoder->power_domain))
>  		return false;
>  
> -	ret = false;
> +	ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
> +				    encoder->port, pipe);
>  
> -	tmp = I915_READ(intel_dp->output_reg);
> -
> -	if (!(tmp & DP_PORT_EN))
> -		goto out;
> -
> -	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> -		*pipe = PORT_TO_PIPE_CPT(tmp);
> -	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> -		enum pipe p;
> -
> -		for_each_pipe(dev_priv, p) {
> -			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
> -			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
> -				*pipe = p;
> -				ret = true;
> -
> -				goto out;
> -			}
> -		}
> -
> -		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
> -			      i915_mmio_reg_offset(intel_dp->output_reg));
> -	} else if (IS_CHERRYVIEW(dev_priv)) {
> -		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
> -	} else {
> -		*pipe = PORT_TO_PIPE(tmp);
> -	}
> -
> -	ret = true;
> -
> -out:
>  	intel_display_power_put(dev_priv, encoder->power_domain);
>  
>  	return ret;
> @@ -3684,8 +3698,9 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
>  
>  		/* always enable with pattern 1 (as per spec) */
> -		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
> -		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
> +		DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
> +		DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
> +			DP_LINK_TRAIN_PAT_1;
>  		I915_WRITE(intel_dp->output_reg, DP);
>  		POSTING_READ(intel_dp->output_reg);
>  
> @@ -5320,14 +5335,14 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
>  static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	enum pipe pipe;
>  
> -	if ((intel_dp->DP & DP_PORT_EN) == 0)
> -		return INVALID_PIPE;
> +	if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
> +				  encoder->port, &pipe))
> +		return pipe;
>  
> -	if (IS_CHERRYVIEW(dev_priv))
> -		return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
> -	else
> -		return PORT_TO_PIPE(intel_dp->DP);
> +	return INVALID_PIPE;
>  }
>  
>  void intel_dp_encoder_reset(struct drm_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a827a2245c18..dc7f81e1e20a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1647,6 +1647,9 @@ void intel_csr_ucode_suspend(struct drm_i915_private *);
>  void intel_csr_ucode_resume(struct drm_i915_private *);
>  
>  /* intel_dp.c */
> +bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
> +			   i915_reg_t dp_reg, enum port port,
> +			   enum pipe *pipe);
>  bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
>  		   enum port port);
>  bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 5/7] drm/i915: Allow eDP on port C in theory

[Jani Nikula]

On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The power sequencer has bits to allow DP C to be used for eDP.
> Currently we assume this will never happen, but I guess it could
> theoretically be a thing. Make the code do the right thing in that
> case, and toss in a MISSING_CASE() for any other port.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index aab48283f155..fdec8f18a52a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5737,10 +5737,20 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		port_sel = PANEL_PORT_SELECT_VLV(port);
>  	} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
> -		if (port == PORT_A)
> +		switch (port) {
> +		case PORT_A:
>  			port_sel = PANEL_PORT_SELECT_DPA;
> -		else
> +			break;
> +		case PORT_C:
> +			port_sel = PANEL_PORT_SELECT_DPC;
> +			break;
> +		case PORT_D:
>  			port_sel = PANEL_PORT_SELECT_DPD;
> +			break;
> +		default:
> +			MISSING_CASE(port);
> +			break;
> +		}
>  	}
>  
>  	pp_on |= port_sel;

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 6/7] drm/i915: Implement the missing bits of assert_panel_unlocked()

[Jani Nikula]

On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add the missing eDP port handling into assert_panel_unlocked(). We now
> have intel_dp_port_enabled() which makes this trivial.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Can we now change the initialization

	enum pipe panel_pipe = PIPE_A;

to

	enum pipe panel_pipe = INVALID_PIPE;

?

> ---
>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d397febb5a7f..a7702a72cd69 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1214,9 +1214,23 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		pp_reg = PP_CONTROL(0);
>  		port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
>  
> -		if (port_sel == PANEL_PORT_SELECT_LVDS)
> +		switch (port_sel) {
> +		case PANEL_PORT_SELECT_LVDS:
>  			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
> -		/* XXX: else fix for eDP */
> +			break;
> +		case PANEL_PORT_SELECT_DPA:
> +			intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
> +			break;
> +		case PANEL_PORT_SELECT_DPC:
> +			intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
> +			break;
> +		case PANEL_PORT_SELECT_DPD:
> +			intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
> +			break;
> +		default:
> +			MISSING_CASE(port_sel);
> +			break;
> +		}
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		/* presumably write lock depends on pipe, not port select */
>  		pp_reg = PP_CONTROL(pipe);

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 7/7] drm/i915: WARN if power sequencer is not connected to the LVDS port on pre-ilk

[Jani Nikula]

On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We don't support using the power sequencer with other ports besides LVDS
> on pre-ilk platforms. WARN if someone has mistakenly connected the power
> sequencer to the wrong port.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a7702a72cd69..4773a4f52bfe 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1236,7 +1236,12 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		pp_reg = PP_CONTROL(pipe);
>  		panel_pipe = pipe;
>  	} else {
> +		u32 port_sel;
> +
>  		pp_reg = PP_CONTROL(0);
> +		port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
> +
> +		WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
>  		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
>  	}

-- 
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Re: [PATCH 6/7] drm/i915: Implement the missing bits of assert_panel_unlocked()

[Ville Syrjälä]

On Wed, May 23, 2018 at 12:42:43PM +0300, Jani Nikula wrote:
> On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add the missing eDP port handling into assert_panel_unlocked(). We now
> > have intel_dp_port_enabled() which makes this trivial.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> Can we now change the initialization
> 
> 	enum pipe panel_pipe = PIPE_A;
> 
> to
> 
> 	enum pipe panel_pipe = INVALID_PIPE;
> 
> ?

Hmm. Yes, I believe we can.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++--
> >  1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index d397febb5a7f..a7702a72cd69 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1214,9 +1214,23 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  		pp_reg = PP_CONTROL(0);
> >  		port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
> >  
> > -		if (port_sel == PANEL_PORT_SELECT_LVDS)
> > +		switch (port_sel) {
> > +		case PANEL_PORT_SELECT_LVDS:
> >  			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
> > -		/* XXX: else fix for eDP */
> > +			break;
> > +		case PANEL_PORT_SELECT_DPA:
> > +			intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
> > +			break;
> > +		case PANEL_PORT_SELECT_DPC:
> > +			intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
> > +			break;
> > +		case PANEL_PORT_SELECT_DPD:
> > +			intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
> > +			break;
> > +		default:
> > +			MISSING_CASE(port_sel);
> > +			break;
> > +		}
> >  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> >  		/* presumably write lock depends on pipe, not port select */
> >  		pp_reg = PP_CONTROL(pipe);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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Re: [PATCH 7/7] drm/i915: WARN if power sequencer is not connected to the LVDS port on pre-ilk

[Ville Syrjälä]

On Wed, May 23, 2018 at 12:43:16PM +0300, Jani Nikula wrote:
> On Fri, 18 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We don't support using the power sequencer with other ports besides LVDS
> > on pre-ilk platforms. WARN if someone has mistakenly connected the power
> > sequencer to the wrong port.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Series pushed to dinq. Thanks for the review.

> 
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a7702a72cd69..4773a4f52bfe 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1236,7 +1236,12 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  		pp_reg = PP_CONTROL(pipe);
> >  		panel_pipe = pipe;
> >  	} else {
> > +		u32 port_sel;
> > +
> >  		pp_reg = PP_CONTROL(0);
> > +		port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
> > +
> > +		WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
> >  		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
> >  	}
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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