[Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU

From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
	frederic.konrad@adacore.com, alistair@alistair23.me,
	frasse.iglesias@gmail.com, sstabellini@kernel.org,
	sai.pavan.boddu@xilinx.com, edgar.iglesias@xilinx.com
Subject: [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU
Date: Thu, 24 May 2018 00:47:45 +0200	[thread overview]
Message-ID: <20180523224745.30402-2-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <20180523224745.30402-1-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Conditionalize setting of PVR11_USE_MMU on the use_mmu
CPU property, otherwise we may incorrectly advertise an
MMU via PVR when the core in fact has none.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/cpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 06476f6efc..a6f1ce6549 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -201,7 +201,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                                         PVR5_DCACHE_WRITEBACK_MASK : 0;
 
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
-    env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
+    env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
+                        16 << 17;
 
     mcc->parent_realize(dev, errp);
 }
-- 
2.14.1
