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From: Mirela Simonovic <mirela.simonovic@aggios.com>
To: xen-devel@lists.xen.org
Cc: edgar.iglesias@xilinx.com, julien.grall@arm.com,
	sstabellini@kernel.org,
	Mirela Simonovic <mirela.simonovic@aggios.com>
Subject: [PATCH v5 01/10] xen/arm64: Added handling of the trapped access to OSLSR register
Date: Fri,  1 Jun 2018 15:17:41 +0200	[thread overview]
Message-ID: <20180601131750.16598-2-mirela.simonovic@aggios.com> (raw)
In-Reply-To: <20180601131750.16598-1-mirela.simonovic@aggios.com>

Linux/dom0 accesses OSLSR register when saving CPU context during the
suspend procedure. Xen traps access to this register, but has no handling
for it. Consequently, Xen injects undef exception to linux, causing it to
crash. This patch adds handling of the trapped access to OSLSR as read
only as a fixed value.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Acked-by: Julien Grall <julien.grall@arm.com>

---
CC: Stefano Stabellini <sstabellini@kernel.org>
CC: Julien Grall <julien.grall@arm.com>
---
Changes in v2:
- Commit message fix (arm64 related change instead of arm)
- Add Stefano's reviewed-by

Changes in v3:
- Added Julien's acked-by

Changes in v5:
-Insted of zero the reading of OSLSR_EL1 should return set bit 3
-Implement new helper handle_ro_read_val() to support read only as a value.
 handle_ro_read_val() reuses the implementation of handle_ro_raz() and
 extends it with additional argument for passing the value to be returned
-Use handle_ro_read_val() for handle_ro_raz() implementation to avoid code
 duplication
-Fix commit message to reflect changes made in this version
---
 xen/arch/arm/arm64/vsysreg.c |  4 +++-
 xen/arch/arm/traps.c         | 26 ++++++++++++++++++--------
 xen/include/asm-arm/traps.h  |  4 ++++
 3 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
index c57ac12503..6e60824572 100644
--- a/xen/arch/arm/arm64/vsysreg.c
+++ b/xen/arch/arm/arm64/vsysreg.c
@@ -57,13 +57,15 @@ void do_sysreg(struct cpu_user_regs *regs,
      * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
      *
      * Unhandled:
-     *    OSLSR_EL1
      *    DBGPRCR_EL1
      */
     case HSR_SYSREG_OSLAR_EL1:
         return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
     case HSR_SYSREG_OSDLR_EL1:
         return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
+    case HSR_SYSREG_OSLSR_EL1:
+        return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 1,
+                                  1 << 3);
 
     /*
      * MDCR_EL2.TDA
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 5c18e918b0..d71adfa745 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1739,12 +1739,13 @@ void handle_wo_wi(struct cpu_user_regs *regs,
     advance_pc(regs, hsr);
 }
 
-/* Read only as read as zero */
-void handle_ro_raz(struct cpu_user_regs *regs,
-                   int regidx,
-                   bool read,
-                   const union hsr hsr,
-                   int min_el)
+/* Read only as value provided with 'val' argument of this function */
+void handle_ro_read_val(struct cpu_user_regs *regs,
+                        int regidx,
+                        bool read,
+                        const union hsr hsr,
+                        int min_el,
+                        register_t val)
 {
     ASSERT((min_el == 0) || (min_el == 1));
 
@@ -1753,13 +1754,22 @@ void handle_ro_raz(struct cpu_user_regs *regs,
 
     if ( !read )
         return inject_undef_exception(regs, hsr);
-    /* else: raz */
 
-    set_user_reg(regs, regidx, 0);
+    set_user_reg(regs, regidx, val);
 
     advance_pc(regs, hsr);
 }
 
+/* Read only as read as zero */
+inline void handle_ro_raz(struct cpu_user_regs *regs,
+                          int regidx,
+                          bool read,
+                          const union hsr hsr,
+                          int min_el)
+{
+    handle_ro_read_val(regs, regidx, read, hsr, min_el, 0);
+}
+
 void dump_guest_s1_walk(struct domain *d, vaddr_t addr)
 {
     register_t ttbcr = READ_SYSREG(TCR_EL1);
diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h
index a0e5e92ebb..70b52d1d16 100644
--- a/xen/include/asm-arm/traps.h
+++ b/xen/include/asm-arm/traps.h
@@ -27,6 +27,10 @@ void handle_wo_wi(struct cpu_user_regs *regs, int regidx, bool read,
 void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read,
                    const union hsr hsr, int min_el);
 
+/* Read only as value provided with 'val' argument */
+void handle_ro_read_val(struct cpu_user_regs *regs, int regidx, bool read,
+                        const union hsr hsr, int min_el, register_t val);
+
 /* Co-processor registers emulation (see arch/arm/vcpreg.c). */
 void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr);
 void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr);
-- 
2.13.0


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  reply	other threads:[~2018-06-01 13:17 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-01 13:17 [PATCH v5 00/10] xen/arm64: Suspend preconditions and CPU hotplug fixes Mirela Simonovic
2018-06-01 13:17 ` Mirela Simonovic [this message]
2018-06-05 17:24   ` [PATCH v5 01/10] xen/arm64: Added handling of the trapped access to OSLSR register Julien Grall
2018-06-05 18:00     ` Julien Grall
2018-06-07 10:54       ` Mirela Simonovic
2018-06-01 13:17 ` [PATCH v5 02/10] xen/arm: Ignore write to GICD_ISACTIVERn registers (vgic-v2) Mirela Simonovic
2018-06-01 13:17 ` [PATCH v5 03/10] xen/arm: Implement CPU_OFF PSCI call (physical interface) Mirela Simonovic
2018-06-01 13:17 ` [PATCH v5 04/10] xen/arm: Remove __initdata and __init to enable CPU hotplug Mirela Simonovic
2018-06-01 13:17 ` [PATCH v5 05/10] xen/arm: Setup virtual paging for non-boot CPUs on hotplug/resume Mirela Simonovic
2018-06-05 17:25   ` Julien Grall
2018-06-01 13:17 ` [PATCH v5 06/10] xen/common: Restore IRQ affinity when hotplugging a pCPU Mirela Simonovic
2018-06-01 13:17 ` [PATCH v5 07/10] xen/arm: Release maintenance interrupt when CPU is hot-unplugged Mirela Simonovic
2018-06-01 13:17 ` [PATCH v5 08/10] xen/arm: Disable timers and release their interrupts on CPU hot-unplug Mirela Simonovic
2018-06-01 13:17 ` [PATCH v5 09/10] xen/arm: Free memory allocated for sibling/core maps " Mirela Simonovic
2018-06-01 13:17 ` [PATCH v5 10/10] xen/arm: Enable errata for secondary CPU on hotplug after the boot Mirela Simonovic
2018-06-05 18:15 ` [PATCH v5 00/10] xen/arm64: Suspend preconditions and CPU hotplug fixes Julien Grall

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