From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from localhost ([127.0.0.1] helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtp (Exim 4.80) (envelope-from ) id 1fQeAa-0005Rr-Gg for speck@linutronix.de; Wed, 06 Jun 2018 21:32:32 +0200 Message-ID: <20180606192807.929619226@linutronix.de> Date: Wed, 06 Jun 2018 21:27:26 +0200 From: Thomas Gleixner Subject: [patch V2 12/12] x86/apic: Ignore secondary threads if nosmt=force References: <20180606192714.754943543@linutronix.de> MIME-Version: 1 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: Subject: [patch V2 12/12] x86/apic: Ignore secondary threads if nosmt=force From: Thomas Gleixner nosmt on the kernel command line merily prevents the onlining of the secondary SMT siblings. nosmt=force makes the APIC detection code ignore the secondary SMT siblings completely, so they even do not show up as possible CPUs. This is more or less equivalent to disabling SMT in the BIOS. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 2 ++ arch/x86/kernel/acpi/boot.c | 3 ++- arch/x86/kernel/apic/apic.c | 21 ++++++++++++++++++++- 3 files changed, 24 insertions(+), 2 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -502,8 +502,10 @@ extern int default_check_phys_apicid_pre #ifdef CONFIG_SMP bool apic_id_is_primary_thread(unsigned int id); +bool apic_id_disabled(unsigned int id); #else static inline bool apic_id_is_primary_thread(unsigned int id) { return false; } +static inline bool apic_id_disabled(unsigned int id) { return false; } #endif extern void irq_enter(void); --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -181,7 +181,8 @@ static int acpi_register_lapic(int id, u } if (!enabled) { - ++disabled_cpus; + if (!apic_id_disabled(id)) + ++disabled_cpus; return -EINVAL; } --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2200,10 +2200,20 @@ bool apic_id_is_primary_thread(unsigned if (smp_num_siblings == 1) return true; /* Isolate the SMT bit(s) in the APICID and check for 0 */ - mask = (1U << fls(smp_num_siblings) - 1) - 1; + mask = (1U << (fls(smp_num_siblings) - 1)) - 1; return !(apicid & mask); } +/** + * apic_id_disabled - Check whether APIC ID is disabled via SMT control + * @id: APIC ID to check + */ +bool apic_id_disabled(unsigned int id) +{ + return (cpu_smt_control == CPU_SMT_FORCE_DISABLED && + !apic_id_is_primary_thread(id)); +} + /* * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids * and cpuid_to_apicid[] synchronized. @@ -2299,6 +2309,15 @@ int generic_processor_info(int apicid, i return -EINVAL; } + /* + * If SMT is force disabled and the APIC ID belongs to + * a secondary thread, ignore it. + */ + if (apic_id_disabled(apicid)) { + pr_info_once("Ignoring secondary SMT threads\n"); + return -EINVAL; + } + if (apicid == boot_cpu_physical_apicid) { /* * x86_bios_cpu_apicid is required to have processors listed