From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sebastian Reichel Subject: Re: [PATCH v2 56/60] drm/omap: Store CRTC lookup by channel table in omap_drm_private Date: Mon, 11 Jun 2018 14:00:17 +0200 Message-ID: <20180611120017.kwyjb4o27z4fo3bk@earth.universe> References: <20180526172518.18710-1-laurent.pinchart@ideasonboard.com> <20180526172518.18710-57-laurent.pinchart@ideasonboard.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0176034448==" Return-path: Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id EF2126E322 for ; Mon, 11 Jun 2018 12:00:19 +0000 (UTC) In-Reply-To: <20180526172518.18710-57-laurent.pinchart@ideasonboard.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Laurent Pinchart Cc: Tomi Valkeinen , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0176034448== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="3s4niaw6pqcf2bfy" Content-Disposition: inline --3s4niaw6pqcf2bfy Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Sat, May 26, 2018 at 08:25:14PM +0300, Laurent Pinchart wrote: > The omap_crtcs global array is used to store pointers to omap_crtc > indexed by DISPC channel number, in order to look them up in the dss_mgr > operations. Store the information in the omap_drm_private structure in > the form of an array of omap_drm_pipeline pointers. >=20 > Signed-off-by: Laurent Pinchart > --- Reviewed-by: Sebastian Reichel -- Sebastian > drivers/gpu/drm/omapdrm/omap_crtc.c | 22 +++++++++------------- > drivers/gpu/drm/omapdrm/omap_drv.c | 19 +++++++++++++++++++ > drivers/gpu/drm/omapdrm/omap_drv.h | 1 + > 3 files changed, 29 insertions(+), 13 deletions(-) >=20 > diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdr= m/omap_crtc.c > index f5bdb8de98f4..9742d9f49a7c 100644 > --- a/drivers/gpu/drm/omapdrm/omap_crtc.c > +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c > @@ -109,7 +109,6 @@ int omap_crtc_wait_pending(struct drm_crtc *crtc) > */ > =20 > /* ovl-mgr-id -> crtc */ > -static struct omap_crtc *omap_crtcs[8]; > static struct omap_dss_device *omap_crtc_output[8]; > =20 > /* we can probably ignore these until we support command-mode panels: */ > @@ -215,7 +214,8 @@ static void omap_crtc_set_enabled(struct drm_crtc *cr= tc, bool enable) > static int omap_crtc_dss_enable(struct omap_drm_private *priv, > enum omap_channel channel) > { > - struct omap_crtc *omap_crtc =3D omap_crtcs[channel]; > + struct drm_crtc *crtc =3D priv->channels[channel]->crtc; > + struct omap_crtc *omap_crtc =3D to_omap_crtc(crtc); > =20 > priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel, > &omap_crtc->vm); > @@ -227,7 +227,8 @@ static int omap_crtc_dss_enable(struct omap_drm_priva= te *priv, > static void omap_crtc_dss_disable(struct omap_drm_private *priv, > enum omap_channel channel) > { > - struct omap_crtc *omap_crtc =3D omap_crtcs[channel]; > + struct drm_crtc *crtc =3D priv->channels[channel]->crtc; > + struct omap_crtc *omap_crtc =3D to_omap_crtc(crtc); > =20 > omap_crtc_set_enabled(&omap_crtc->base, false); > } > @@ -236,7 +237,9 @@ static void omap_crtc_dss_set_timings(struct omap_drm= _private *priv, > enum omap_channel channel, > const struct videomode *vm) > { > - struct omap_crtc *omap_crtc =3D omap_crtcs[channel]; > + struct drm_crtc *crtc =3D priv->channels[channel]->crtc; > + struct omap_crtc *omap_crtc =3D to_omap_crtc(crtc); > + > DBG("%s", omap_crtc->name); > omap_crtc->vm =3D *vm; > } > @@ -245,7 +248,8 @@ static void omap_crtc_dss_set_lcd_config(struct omap_= drm_private *priv, > enum omap_channel channel, > const struct dss_lcd_mgr_config *config) > { > - struct omap_crtc *omap_crtc =3D omap_crtcs[channel]; > + struct drm_crtc *crtc =3D priv->channels[channel]->crtc; > + struct omap_crtc *omap_crtc =3D to_omap_crtc(crtc); > =20 > DBG("%s", omap_crtc->name); > priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel, > @@ -681,8 +685,6 @@ static const char *channel_names[] =3D { > =20 > void omap_crtc_pre_init(struct omap_drm_private *priv) > { > - memset(omap_crtcs, 0, sizeof(omap_crtcs)); > - > dss_install_mgr_ops(priv->dss, &mgr_ops, priv); > } > =20 > @@ -706,10 +708,6 @@ struct drm_crtc *omap_crtc_init(struct drm_device *d= ev, > =20 > DBG("%s", channel_names[channel]); > =20 > - /* Multiple displays on same channel is not allowed */ > - if (WARN_ON(omap_crtcs[channel] !=3D NULL)) > - return ERR_PTR(-EINVAL); > - > omap_crtc =3D kzalloc(sizeof(*omap_crtc), GFP_KERNEL); > if (!omap_crtc) > return ERR_PTR(-ENOMEM); > @@ -748,7 +746,5 @@ struct drm_crtc *omap_crtc_init(struct drm_device *de= v, > =20 > omap_plane_install_properties(crtc->primary, &crtc->base); > =20 > - omap_crtcs[channel] =3D omap_crtc; > - > return crtc; > } > diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm= /omap_drv.c > index 6bc826515684..c3c657d90029 100644 > --- a/drivers/gpu/drm/omapdrm/omap_drv.c > +++ b/drivers/gpu/drm/omapdrm/omap_drv.c > @@ -167,6 +167,8 @@ static void omap_disconnect_pipelines(struct drm_devi= ce *ddev) > pipe->display =3D NULL; > } > =20 > + memset(&priv->channels, 0, sizeof(priv->channels)); > + > priv->num_pipes =3D 0; > } > =20 > @@ -186,6 +188,7 @@ static int omap_connect_pipelines(struct drm_device *= ddev) > { > struct omap_drm_private *priv =3D ddev->dev_private; > struct omap_dss_device *output =3D NULL; > + unsigned int i; > int r; > =20 > if (!omapdss_stack_is_ready()) > @@ -218,6 +221,22 @@ static int omap_connect_pipelines(struct drm_device = *ddev) > sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]), > omap_compare_pipes, NULL); > =20 > + /* > + * Populate the pipeline lookup table by DISPC channel. Only one display > + * is allowed per channel. > + */ > + for (i =3D 0; i < priv->num_pipes; ++i) { > + struct omap_drm_pipeline *pipe =3D &priv->pipes[i]; > + enum omap_channel channel =3D pipe->output->dispc_channel; > + > + if (WARN_ON(priv->channels[channel] !=3D NULL)) { > + r =3D -EINVAL; > + goto cleanup; > + } > + > + priv->channels[channel] =3D pipe; > + } > + > return 0; > =20 > cleanup: > diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm= /omap_drv.h > index a38d07d4d6ea..bd7f2c227a25 100644 > --- a/drivers/gpu/drm/omapdrm/omap_drv.h > +++ b/drivers/gpu/drm/omapdrm/omap_drv.h > @@ -64,6 +64,7 @@ struct omap_drm_private { > =20 > unsigned int num_pipes; > struct omap_drm_pipeline pipes[8]; > + struct omap_drm_pipeline *channels[8]; > =20 > unsigned int num_planes; > struct drm_plane *planes[8]; > --=20 > Regards, >=20 > Laurent Pinchart >=20 > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel --3s4niaw6pqcf2bfy Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAlseZFEACgkQ2O7X88g7 +pqqPw/+Jrc4KX+SNAA0thbcuXgqYzYqr1Bw0Vl//XOKSeFMR4zZt8b/0mMU74DG Dxgp1KpYBXbx9GHuWmiKw+ZVNgaGkzAtskiXz+fmxTsdaGBY4p+xjhOXgrDdxtTo jdATRLno+5DqBoRa8VQBmzZZofG2wsEbT222lBUKR/hf5j/bMfhUruTbKkmLeKDS M7LQ1v0yXRAHsHzPlR8pLb74Tb6NA4rp1LROryh0E0j87cU3tpzsHWeD4TyKneWR /nZR0QZRgyQOT8QzkS97MMlZjGPFsuFT8KbP/Jzr80kpkYSNUTYGtW7JHJoTSMot 5Z82zJ1f1y1+nPJS+HC6ykWzEi0KPyqngBdHvWVUAb7HQAzR2EiNbhVQ+v+hAd9K 1kJmI4SOq9P4bWY7lRZeMC+CfWkxallqYQcmIQZ0eRqm4OcMwmXZuF+4gdyPTnTb 3d2h88B5IYwyd3FOn3YDdQaPYlF4dZFStC2mCQc1KVLkfk+pS/cfQMlLmOQkP90c HeHon33rTm14djgFuCbGJ1T0ly1xQ+FMM1hyA7DEAh+JcyZ86p9sXvqxURfI6yxq Pza2RLjO/hyvl5yq8tY3rRsXlTGDnBdfwqR0ukYKP4BzOo5Y8k/yKLVijF7z2+uT /GK5a6uLPNCl7JLhipy4Uu+QiT+uYUk5UnhL/Ml4TxXrqsJ7Rv4= =8hga -----END PGP SIGNATURE----- --3s4niaw6pqcf2bfy-- --===============0176034448== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============0176034448==--