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From: Jernej Skrabec <jernej.skrabec@siol.net>
To: maxime.ripard@bootlin.com, wens@csie.org, robh+dt@kernel.org
Cc: airlied@linux.ie, gustavo@padovan.org,
	maarten.lankhorst@linux.intel.com, seanpaul@chromium.org,
	mark.rutland@arm.com, dri-devel@lists.freedesktop.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-sunxi@googlegroups.com
Subject: [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs
Date: Tue, 12 Jun 2018 22:00:10 +0200	[thread overview]
Message-ID: <20180612200036.21483-2-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>

According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.

Because of that, set minimal rate to both R40 video PLLs to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 46 +++++++++++++++-------------
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..c16a62a7bdbd 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -65,17 +65,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
 				   CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
-					"osc24M", 0x0010,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+					    "osc24M", 0x0010,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
@@ -151,17 +152,18 @@ static struct ccu_nk pll_periph1_clk = {
 };
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
-					"osc24M", 0x030,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+					    "osc24M", 0x030,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 static struct ccu_nkm pll_sata_clk = {
 	.enable		= BIT(31),
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org,
	wens-jdAy2FN1RRM@public.gmane.org,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: airlied-cv59FeDIM0c@public.gmane.org,
	gustavo-THi1TnShQwVAfugRpC6u6w@public.gmane.org,
	maarten.lankhorst-VuQAYsv1563Yd54FQh9/CA@public.gmane.org,
	seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs
Date: Tue, 12 Jun 2018 22:00:10 +0200	[thread overview]
Message-ID: <20180612200036.21483-2-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20180612200036.21483-1-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>

According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.

Because of that, set minimal rate to both R40 video PLLs to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 46 +++++++++++++++-------------
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..c16a62a7bdbd 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -65,17 +65,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
 				   CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
-					"osc24M", 0x0010,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+					    "osc24M", 0x0010,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
@@ -151,17 +152,18 @@ static struct ccu_nk pll_periph1_clk = {
 };
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
-					"osc24M", 0x030,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+					    "osc24M", 0x030,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 static struct ccu_nkm pll_sata_clk = {
 	.enable		= BIT(31),
-- 
2.17.1

WARNING: multiple messages have this Message-ID (diff)
From: Jernej Skrabec <jernej.skrabec@siol.net>
To: maxime.ripard@bootlin.com, wens@csie.org, robh+dt@kernel.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
	airlied@linux.ie, gustavo@padovan.org,
	maarten.lankhorst@linux.intel.com, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com,
	seanpaul@chromium.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs
Date: Tue, 12 Jun 2018 22:00:10 +0200	[thread overview]
Message-ID: <20180612200036.21483-2-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>

According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.

Because of that, set minimal rate to both R40 video PLLs to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 46 +++++++++++++++-------------
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..c16a62a7bdbd 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -65,17 +65,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
 				   CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
-					"osc24M", 0x0010,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+					    "osc24M", 0x0010,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
@@ -151,17 +152,18 @@ static struct ccu_nk pll_periph1_clk = {
 };
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
-					"osc24M", 0x030,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+					    "osc24M", 0x030,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 static struct ccu_nkm pll_sata_clk = {
 	.enable		= BIT(31),
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: jernej.skrabec@siol.net (Jernej Skrabec)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs
Date: Tue, 12 Jun 2018 22:00:10 +0200	[thread overview]
Message-ID: <20180612200036.21483-2-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>

According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.

Because of that, set minimal rate to both R40 video PLLs to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 46 +++++++++++++++-------------
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..c16a62a7bdbd 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -65,17 +65,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
 				   CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
-					"osc24M", 0x0010,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+					    "osc24M", 0x0010,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
@@ -151,17 +152,18 @@ static struct ccu_nk pll_periph1_clk = {
 };
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
-					"osc24M", 0x030,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+					    "osc24M", 0x030,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 static struct ccu_nkm pll_sata_clk = {
 	.enable		= BIT(31),
-- 
2.17.1

  reply	other threads:[~2018-06-12 20:01 UTC|newest]

Thread overview: 201+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-12 20:00 [PATCH v2 00/27] Add support for R40 HDMI pipeline Jernej Skrabec
2018-06-12 20:00 ` Jernej Skrabec
2018-06-12 20:00 ` Jernej Skrabec
2018-06-12 20:00 ` Jernej Skrabec [this message]
2018-06-12 20:00   ` [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-13  3:18   ` Chen-Yu Tsai
2018-06-13  3:18     ` Chen-Yu Tsai
2018-06-13  3:18     ` Chen-Yu Tsai
2018-06-12 20:00 ` [PATCH v2 02/27] clk: sunxi-ng: r40: Allow setting parent rate to display related clocks Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-13  3:19   ` Chen-Yu Tsai
2018-06-13  3:19     ` Chen-Yu Tsai
2018-06-13  3:19     ` Chen-Yu Tsai
2018-06-12 20:00 ` [PATCH v2 03/27] clk: sunxi-ng: r40: Export video PLLs Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 04/27] dt-bindings: display: sunxi-drm: Add TCON TOP description Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-13  7:34   ` Maxime Ripard
2018-06-13  7:34     ` Maxime Ripard
2018-06-13  7:34     ` Maxime Ripard
2018-06-13 16:03     ` [linux-sunxi] " Jernej Škrabec
2018-06-13 16:03       ` Jernej Škrabec
2018-06-13 16:03       ` Jernej Škrabec
2018-06-15  8:45       ` [linux-sunxi] " Maxime Ripard
2018-06-15  8:45         ` Maxime Ripard
2018-06-15  8:45         ` Maxime Ripard
2018-06-12 20:00 ` [PATCH v2 05/27] drm/sun4i: Add TCON TOP driver Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-13  7:07   ` kbuild test robot
2018-06-13  7:07     ` kbuild test robot
2018-06-13  7:07     ` kbuild test robot
2018-06-12 20:00 ` [PATCH v2 06/27] drm/sun4i: Fix releasing node when enumerating enpoints Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 07/27] drm/sun4i: Split out code for enumerating endpoints in output port Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 08/27] drm/sun4i: Add support for traversing graph with TCON TOP Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 09/27] drm/sun4i: Don't skip TCONs if they don't have channel 0 Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 10/27] dt-bindings: display: sun4i-drm: Add R40 TV TCON description Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-20 19:15   ` Rob Herring
2018-06-20 19:15     ` Rob Herring
2018-06-20 19:15     ` Rob Herring
2018-06-12 20:00 ` [PATCH v2 11/27] drm/sun4i: tcon: Add support for tcon-top gate Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-15  8:31   ` Maxime Ripard
2018-06-15  8:31     ` Maxime Ripard
2018-06-15  8:31     ` Maxime Ripard
2018-06-15 16:41     ` Jernej Škrabec
2018-06-15 16:41       ` Jernej Škrabec
2018-06-15 16:41       ` Jernej Škrabec
2018-06-15 17:13       ` [linux-sunxi] " Chen-Yu Tsai
2018-06-15 17:13         ` Chen-Yu Tsai
2018-06-15 17:13         ` Chen-Yu Tsai
2018-06-15 17:33         ` [linux-sunxi] " Jernej Škrabec
2018-06-15 17:33           ` Jernej Škrabec
2018-06-15 17:33           ` Jernej Škrabec
2018-06-16  5:48           ` [linux-sunxi] " Chen-Yu Tsai
2018-06-16  5:48             ` Chen-Yu Tsai
2018-06-16  5:48             ` Chen-Yu Tsai
2018-06-20 19:37             ` [linux-sunxi] " Jernej Škrabec
2018-06-20 19:37               ` Jernej Škrabec
2018-06-20 19:37               ` Jernej Škrabec
2018-06-21  1:23               ` [linux-sunxi] " Chen-Yu Tsai
2018-06-21  1:23                 ` Chen-Yu Tsai
2018-06-21  1:23                 ` Chen-Yu Tsai
2018-06-21 15:35                 ` [linux-sunxi] " Jernej Škrabec
2018-06-21 15:35                   ` Jernej Škrabec
2018-06-21 15:35                   ` Jernej Škrabec
2018-06-24 19:52                   ` [linux-sunxi] " Jernej Škrabec
2018-06-24 19:52                     ` Jernej Škrabec
2018-06-24 19:52                     ` Jernej Škrabec
2018-06-24 19:52                     ` Jernej Škrabec
2018-06-25  3:51                     ` [linux-sunxi] " Chen-Yu Tsai
2018-06-25  3:51                       ` Chen-Yu Tsai
2018-06-25  3:51                       ` Chen-Yu Tsai
2018-06-25  7:58                       ` [linux-sunxi] " Jernej Škrabec
2018-06-25  7:58                         ` Jernej Škrabec
2018-06-25  7:58                         ` Jernej Škrabec
2018-06-25  7:58                         ` Jernej Škrabec
2018-06-25  8:14                         ` [linux-sunxi] " Chen-Yu Tsai
2018-06-25  8:14                           ` Chen-Yu Tsai
2018-06-25  8:14                           ` Chen-Yu Tsai
2018-06-25  9:10                           ` [linux-sunxi] " Jernej Škrabec
2018-06-25  9:10                             ` Jernej Škrabec
2018-06-25  9:10                             ` Jernej Škrabec
2018-06-25  9:10                             ` Jernej Škrabec
2018-06-12 20:00 ` [PATCH v2 12/27] drm/sun4i: tcon: Generalize engine search algorithm Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 13/27] drm/sun4i: Don't check for LVDS and RGB when TCON has only ch1 Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 14/27] drm/sun4i: Don't check for panel or bridge on TV TCONs Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-13  7:46   ` Maxime Ripard
2018-06-13  7:46     ` Maxime Ripard
2018-06-13  7:46     ` Maxime Ripard
2018-06-13  8:04     ` Chen-Yu Tsai
2018-06-13  8:04       ` Chen-Yu Tsai
2018-06-13  8:04       ` Chen-Yu Tsai
2018-06-13 16:20       ` [linux-sunxi] " Jernej Škrabec
2018-06-13 16:20         ` Jernej Škrabec
2018-06-13 16:20         ` Jernej Škrabec
2018-06-12 20:00 ` [PATCH v2 15/27] drm/sun4i: Add support for R40 TV TCON Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 16/27] dt-bindings: display: sun4i-drm: Add R40 mixer compatibles Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-20 19:16   ` Rob Herring
2018-06-20 19:16     ` Rob Herring
2018-06-20 19:16     ` Rob Herring
2018-06-12 20:00 ` [PATCH v2 17/27] drm/sun4i: Add support for R40 mixers Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 18/27] dt-bindings: display: sun4i-drm: Add description of A64 HDMI PHY Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-20 19:17   ` Rob Herring
2018-06-20 19:17     ` Rob Herring
2018-06-20 19:17     ` Rob Herring
2018-06-12 20:00 ` [PATCH v2 19/27] drm/sun4i: Enable DW HDMI PHY clock Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 20/27] drm/sun4i: Don't change clock bits in DW HDMI PHY driver Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-15 16:44   ` [linux-sunxi] " Jernej Škrabec
2018-06-15 16:44     ` Jernej Škrabec
2018-06-15 16:44     ` Jernej Škrabec
2018-06-12 20:00 ` [PATCH v2 21/27] drm/sun4i: DW HDMI PHY: Add support for second PLL Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 22/27] drm/sun4i: Add support for second clock parent to DW HDMI PHY clk driver Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 23/27] drm/sun4i: Add support for A64 HDMI PHY Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 24/27] drm: of: Export drm_crtc_port_mask() Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-13  7:36   ` Maxime Ripard
2018-06-13  7:36     ` Maxime Ripard
2018-06-13  7:36     ` Maxime Ripard
2018-06-13 16:04     ` [linux-sunxi] " Jernej Škrabec
2018-06-13 16:04       ` Jernej Škrabec
2018-06-13 16:04       ` Jernej Škrabec
2018-06-12 20:00 ` [PATCH v2 25/27] drm/sun4i: DW HDMI: Expand algorithm for possible crtcs Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 26/27] ARM: dts: sun8i: r40: Add HDMI pipeline Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00 ` [PATCH v2 27/27] ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-12 20:00   ` Jernej Skrabec
2018-06-14  7:12 ` [linux-sunxi] [PATCH v2 00/27] Add support for R40 HDMI pipeline Jagan Teki
2018-06-14  7:12   ` Jagan Teki
2018-06-14  7:12   ` Jagan Teki
2018-06-14 14:34   ` [linux-sunxi] " Jernej Škrabec
2018-06-14 14:34     ` Jernej Škrabec
2018-06-14 14:34     ` Jernej Škrabec
2018-06-14 17:16     ` [linux-sunxi] " Jagan Teki
2018-06-14 17:16       ` Jagan Teki
2018-06-14 17:16       ` Jagan Teki
2018-06-14 17:16       ` Jagan Teki
2018-06-14 17:29       ` [linux-sunxi] " Jernej Škrabec
2018-06-14 17:29         ` Jernej Škrabec
2018-06-14 17:29         ` Jernej Škrabec
2018-06-18 12:58         ` [linux-sunxi] " Jagan Teki
2018-06-18 12:58           ` Jagan Teki
2018-06-18 12:58           ` Jagan Teki
2018-06-18 12:58           ` Jagan Teki
2018-06-18 14:43           ` [linux-sunxi] " Jernej Škrabec
2018-06-18 14:43             ` Jernej Škrabec
2018-06-18 14:43             ` Jernej Škrabec
2018-06-18 18:49             ` [linux-sunxi] " Icenowy Zheng
2018-06-18 18:49               ` Icenowy Zheng
2018-06-18 18:49               ` Icenowy Zheng

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