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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/3] drm/i915: Check timings against hardware maximums
Date: Fri, 15 Jun 2018 20:44:05 +0300	[thread overview]
Message-ID: <20180615174406.12258-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20180615174406.12258-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Validate that all display timings fit within the number of bits
we have in the transcoder timing registers.

The limits are:
hsw+:
 4k: vdisplay, vblank_start
 8k: everything else
gen3+:
 4k: h/vdisplay, h/vblank_start
 8k: everything else
gen2:
 2k: h/vdisplay, h/vblank_start
 4k: everything else

Also document the fact that the mode_config.max_width/height limits
refer to just the max framebuffer dimensions we support. Which may
be larger than the max hdisplay/vdisplay.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f6655f482b67..6e3aa6815b30 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14572,6 +14572,10 @@ static enum drm_mode_status
 intel_mode_valid(struct drm_device *dev,
 		 const struct drm_display_mode *mode)
 {
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int hdisplay_max, htotal_max;
+	int vdisplay_max, vtotal_max;
+
 	/*
 	 * Can't reject DBLSCAN here because Xorg ddxen can add piles
 	 * of DBLSCAN modes to the output's mode list when they detect
@@ -14601,6 +14605,36 @@ intel_mode_valid(struct drm_device *dev,
 			   DRM_MODE_FLAG_CLKDIV2))
 		return MODE_BAD;
 
+	if (INTEL_GEN(dev_priv) >= 9 ||
+	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
+		vdisplay_max = 4096;
+		htotal_max = 8192;
+		vtotal_max = 8192;
+	} else if (INTEL_GEN(dev_priv) >= 3) {
+		hdisplay_max = 4096;
+		vdisplay_max = 4096;
+		htotal_max = 8192;
+		vtotal_max = 8192;
+	} else {
+		hdisplay_max = 2048;
+		vdisplay_max = 2048;
+		htotal_max = 4096;
+		vtotal_max = 4096;
+	}
+
+	if (mode->hdisplay > hdisplay_max ||
+	    mode->hsync_start > htotal_max ||
+	    mode->hsync_end > htotal_max ||
+	    mode->htotal > htotal_max)
+		return MODE_H_ILLEGAL;
+
+	if (mode->vdisplay > vdisplay_max ||
+	    mode->vsync_start > vtotal_max ||
+	    mode->vsync_end > vtotal_max ||
+	    mode->vtotal > vtotal_max)
+		return MODE_V_ILLEGAL;
+
 	return MODE_OK;
 }
 
@@ -15039,6 +15073,7 @@ int intel_modeset_init(struct drm_device *dev)
 		}
 	}
 
+	/* maximum framebuffer dimensions */
 	if (IS_GEN2(dev_priv)) {
 		dev->mode_config.max_width = 2048;
 		dev->mode_config.max_height = 2048;
-- 
2.16.4

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  reply	other threads:[~2018-06-15 17:44 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-15 17:44 [PATCH 1/3] drm/i915: Nuke the cursor size defines Ville Syrjala
2018-06-15 17:44 ` Ville Syrjala [this message]
2018-06-15 18:44   ` [PATCH 2/3] drm/i915: Check timings against hardware maximums Chris Wilson
2018-06-15 19:48     ` Ville Syrjälä
2018-06-15 20:02       ` Chris Wilson
2018-06-15 20:18         ` Ville Syrjälä
2018-06-15 20:30   ` Paulo Zanoni
2018-06-15 20:46     ` Ville Syrjälä
2018-06-15 17:44 ` [PATCH 3/3] drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI Ville Syrjala
2018-06-15 21:09   ` Paulo Zanoni
2018-06-18 13:13     ` Ville Syrjälä
2018-06-15 18:13 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Nuke the cursor size defines Patchwork
2018-06-15 19:49 ` [PATCH 1/3] " Paulo Zanoni
2018-06-16  6:27 ` ✗ Fi.CI.IGT: failure for series starting with [1/3] " Patchwork
2018-06-19 22:17 ` [PATCH 1/3] " Rodrigo Vivi

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