On Mon, Jun 18, 2018 at 01:30:13PM +0200, Cédric Le Goater wrote: > On 06/18/2018 12:38 PM, David Gibson wrote: > > On Fri, Jun 15, 2018 at 05:25:35PM +0200, Cédric Le Goater wrote: > >> This is a major reshuffle of the PowerNV machine and chip models to > >> introduce a machine type per processor. It is quite noisy but it > >> doesn't change much the code flow. > >> > >> It introduces a base PnvChip class from which the specific processor > >> chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to > >> define an init and a realize routine which will create the controllers > >> of the target processor. For the moment, the base PnvChip class > >> handles the XSCOM bus and the cores but the core creation will surely > >> move to the specific processor chip classes because of the new XIVE > >> interrupt controller in Power9. > >> > >> >From there, we introduce two different machines : "powernv8" and > >> "powernv9" but, a part from the XICSFabric interface, this is not > >> strictly needed as it is the cpu type which determines the PnvChip > >> class. Something to discuss. > > > > Yeah.. I'd leave this bit out for now. It can go into a later patch, > > with the machine type actually determining the chip type. > > yes. There are other issues to fix around the machine type anyway. Like > making sure we cannot start a machine with : -M powernv9 -cpu POWER8 > > >> Signed-off-by: Cédric Le Goater > >> --- > >> include/hw/ppc/pnv.h | 23 +++- > >> hw/ppc/pnv.c | 322 +++++++++++++++++++++++++++++++++------------------ > >> 2 files changed, 231 insertions(+), 114 deletions(-) > >> > >> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > >> index 563279f3e00c..244856414580 100644 > >> --- a/include/hw/ppc/pnv.h > >> +++ b/include/hw/ppc/pnv.h > >> @@ -57,12 +57,32 @@ typedef struct PnvChip { > >> MemoryRegion xscom_mmio; > >> MemoryRegion xscom; > >> AddressSpace xscom_as; > >> +} PnvChip; > >> + > >> +#define TYPE_PNV8_CHIP "pnv8-chip" > >> +#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) > >> + > >> +typedef struct Pnv8Chip { > >> + /*< private >*/ > >> + PnvChip parent_obj; > >> + > >> + /*< public >*/ > >> MemoryRegion icp_mmio; > >> > >> PnvLpcController lpc; > >> PnvPsi psi; > >> PnvOCC occ; > >> -} PnvChip; > >> +} Pnv8Chip; > >> + > >> +#define TYPE_PNV9_CHIP "pnv9-chip" > >> +#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) > >> + > >> +typedef struct Pnv9Chip { > >> + /*< private >*/ > >> + PnvChip parent_obj; > >> + > >> + /*< public >*/ > >> +} Pnv9Chip; > >> > >> typedef struct PnvChipClass { > >> /*< private >*/ > >> @@ -75,6 +95,7 @@ typedef struct PnvChipClass { > >> > >> hwaddr xscom_base; > >> > >> + void (*realize)(PnvChip *chip, Error **errp); > > > > This looks the wrong way round from how things are usually done. > > Rather than having the base class realize() call the subclass specific > > realize hook, it's more usual for the subclass to set the > > dc->realize() and have it call a k->parent_realize() to call up the > > chain. grep for device_class_set_parent_realize() for some more > > examples. > > Ah. That is more to my liking. There are a couple of models following > the wrong object pattern, xics, vio. I will check them. Ah, yeah, probably my ignorance at the time showing. > > As a general rule, giving the overall control flow to the most > > specific subclass in the chain tends to work better. > > yes. > > > Other than that, this looks good. > > OK. I will then reshuffle the patchset and move out of the physmap patch > on which we don't seem to have the same ideas. It can come later. > > After that round, the P8/phb3 and P9/Xive can be the next models. > > phb3 would be a good extension to the existing machine. It did some > code rework, so it looks better. > > and Xive is a must of have for P9. But to get a P9 machine running, > we need a couple of more models : > > PSI, LPC, OCC, > > nothing complex, and I think they are ready, and some P9 CPU work: > > 32bit decrementer, stop_lite state, radix. > > I worked around these for the moment. > > Thanks, > > C. > > >> uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); > >> Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); > >> ISABus *(*isa_create)(PnvChip *chip, Error **errp); > >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > >> index ac828d133173..b416a1a6ed63 100644 > >> --- a/hw/ppc/pnv.c > >> +++ b/hw/ppc/pnv.c > >> @@ -531,12 +531,14 @@ static void pnv_reset(void) > >> > >> static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) > >> { > >> - return pnv_lpc_isa_create(&chip->lpc, true, errp); > >> + Pnv8Chip *chip8 = PNV8_CHIP(chip); > >> + return pnv_lpc_isa_create(&chip8->lpc, true, errp); > >> } > >> > >> static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) > >> { > >> - return pnv_lpc_isa_create(&chip->lpc, false, errp); > >> + Pnv8Chip *chip8 = PNV8_CHIP(chip); > >> + return pnv_lpc_isa_create(&chip8->lpc, false, errp); > >> } > >> > >> static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) > >> @@ -725,6 +727,97 @@ static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child, > >> */ > >> #define POWER9_CORE_MASK (0xffffffffffffffull) > >> > >> +static void pnv_chip_power8_instance_init(Object *obj) > >> +{ > >> + Pnv8Chip *chip8 = PNV8_CHIP(obj); > >> + > >> + object_initialize(&chip8->lpc, sizeof(chip8->lpc), TYPE_PNV_LPC); > >> + object_property_add_child(obj, "lpc", OBJECT(&chip8->lpc), NULL); > >> + > >> + object_initialize(&chip8->psi, sizeof(chip8->psi), TYPE_PNV_PSI); > >> + object_property_add_child(obj, "psi", OBJECT(&chip8->psi), NULL); > >> + object_property_add_const_link(OBJECT(&chip8->psi), "xics", > >> + OBJECT(qdev_get_machine()), &error_abort); > >> + > >> + object_initialize(&chip8->occ, sizeof(chip8->occ), TYPE_PNV_OCC); > >> + object_property_add_child(obj, "occ", OBJECT(&chip8->occ), NULL); > >> + object_property_add_const_link(OBJECT(&chip8->occ), "psi", > >> + OBJECT(&chip8->psi), &error_abort); > >> + > >> + /* The LPC controller needs PSI to generate interrupts */ > >> + object_property_add_const_link(OBJECT(&chip8->lpc), "psi", > >> + OBJECT(&chip8->psi), &error_abort); > >> +} > >> + > >> +static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) > >> + { > >> + PnvChip *chip = PNV_CHIP(chip8); > >> + PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); > >> + const char *typename = pnv_chip_core_typename(chip); > >> + size_t typesize = object_type_get_instance_size(typename); > >> + int i, j; > >> + char *name; > >> + XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); > >> + > >> + name = g_strdup_printf("icp-%x", chip->chip_id); > >> + memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); > >> + sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); > >> + g_free(name); > >> + > >> + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); > >> + > >> + /* Map the ICP registers for each thread */ > >> + for (i = 0; i < chip->nr_cores; i++) { > >> + PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); > >> + int core_hwid = CPU_CORE(pnv_core)->core_id; > >> + > >> + for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { > >> + uint32_t pir = pcc->core_pir(chip, core_hwid) + j; > >> + PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); > >> + > >> + memory_region_add_subregion(&chip8->icp_mmio, pir << 12, > >> + &icp->mmio); > >> + } > >> + } > >> +} > >> + > >> +static void pnv_chip_power8_realize(PnvChip *chip, Error **errp) > >> + { > >> + Pnv8Chip *chip8 = PNV8_CHIP(chip); > >> + Error *error = NULL; > >> + > >> + /* Create LPC controller */ > >> + object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", > >> + &error_fatal); > >> + pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); > >> + > >> + /* Interrupt Management Area. This is the memory region holding > >> + * all the Interrupt Control Presenter (ICP) registers */ > >> + pnv_chip_icp_realize(chip8, &error); > >> + if (error) { > >> + error_propagate(errp, error); > >> + return; > >> + } > >> + > >> + /* Processor Service Interface (PSI) Host Bridge */ > >> + object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), > >> + "bar", &error_fatal); > >> + object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &error); > >> + if (error) { > >> + error_propagate(errp, error); > >> + return; > >> + } > >> + pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_regs); > >> + > >> + /* Create the simplified OCC model */ > >> + object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &error); > >> + if (error) { > >> + error_propagate(errp, error); > >> + return; > >> + } > >> + pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); > >> +} > >> + > >> static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) > >> { > >> DeviceClass *dc = DEVICE_CLASS(klass); > >> @@ -736,6 +829,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) > >> k->core_pir = pnv_chip_core_pir_p8; > >> k->intc_create = pnv_chip_power8_intc_create; > >> k->isa_create = pnv_chip_power8_isa_create; > >> + k->realize = pnv_chip_power8_realize; > >> k->xscom_base = 0x003fc0000000000ull; > >> dc->desc = "PowerNV Chip POWER8E"; > >> } > >> @@ -751,6 +845,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) > >> k->core_pir = pnv_chip_core_pir_p8; > >> k->intc_create = pnv_chip_power8_intc_create; > >> k->isa_create = pnv_chip_power8_isa_create; > >> + k->realize = pnv_chip_power8_realize; > >> k->xscom_base = 0x003fc0000000000ull; > >> dc->desc = "PowerNV Chip POWER8"; > >> } > >> @@ -766,10 +861,20 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) > >> k->core_pir = pnv_chip_core_pir_p8; > >> k->intc_create = pnv_chip_power8_intc_create; > >> k->isa_create = pnv_chip_power8nvl_isa_create; > >> + k->realize = pnv_chip_power8_realize; > >> k->xscom_base = 0x003fc0000000000ull; > >> dc->desc = "PowerNV Chip POWER8NVL"; > >> } > >> > >> +static void pnv_chip_power9_instance_init(Object *obj) > >> +{ > >> +} > >> + > >> +static void pnv_chip_power9_realize(PnvChip *chip, Error **errp) > >> +{ > >> + > >> +} > >> + > >> static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) > >> { > >> DeviceClass *dc = DEVICE_CLASS(klass); > >> @@ -781,6 +886,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) > >> k->core_pir = pnv_chip_core_pir_p9; > >> k->intc_create = pnv_chip_power9_intc_create; > >> k->isa_create = pnv_chip_power9_isa_create; > >> + k->realize = pnv_chip_power9_realize; > >> k->xscom_base = 0x00603fc00000000ull; > >> dc->desc = "PowerNV Chip POWER9"; > >> } > >> @@ -815,59 +921,9 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) > >> } > >> } > >> > >> -static void pnv_chip_init(Object *obj) > >> +static void pnv_chip_instance_init(Object *obj) > >> { > >> - PnvChip *chip = PNV_CHIP(obj); > >> - PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); > >> - > >> - chip->xscom_base = pcc->xscom_base; > >> - > >> - object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); > >> - object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); > >> - > >> - object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); > >> - object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); > >> - object_property_add_const_link(OBJECT(&chip->psi), "xics", > >> - OBJECT(qdev_get_machine()), &error_abort); > >> - > >> - object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); > >> - object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); > >> - object_property_add_const_link(OBJECT(&chip->occ), "psi", > >> - OBJECT(&chip->psi), &error_abort); > >> - > >> - /* The LPC controller needs PSI to generate interrupts */ > >> - object_property_add_const_link(OBJECT(&chip->lpc), "psi", > >> - OBJECT(&chip->psi), &error_abort); > >> -} > >> - > >> -static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) > >> -{ > >> - PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); > >> - const char *typename = pnv_chip_core_typename(chip); > >> - size_t typesize = object_type_get_instance_size(typename); > >> - int i, j; > >> - char *name; > >> - XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); > >> - > >> - name = g_strdup_printf("icp-%x", chip->chip_id); > >> - memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); > >> - sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); > >> - g_free(name); > >> - > >> - sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); > >> - > >> - /* Map the ICP registers for each thread */ > >> - for (i = 0; i < chip->nr_cores; i++) { > >> - PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); > >> - int core_hwid = CPU_CORE(pnv_core)->core_id; > >> - > >> - for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { > >> - uint32_t pir = pcc->core_pir(chip, core_hwid) + j; > >> - PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); > >> - > >> - memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio); > >> - } > >> - } > >> + PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base; > >> } > >> > >> static void pnv_chip_core_realize(PnvChip *chip, Error **errp) > >> @@ -935,6 +991,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) > >> static void pnv_chip_realize(DeviceState *dev, Error **errp) > >> { > >> PnvChip *chip = PNV_CHIP(dev); > >> + PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); > >> Error *error = NULL; > >> > >> /* XSCOM bridge */ > >> @@ -952,36 +1009,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp) > >> return; > >> } > >> > >> - /* Create LPC controller */ > >> - object_property_set_bool(OBJECT(&chip->lpc), true, "realized", > >> - &error_fatal); > >> - pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs); > >> - > >> - /* Interrupt Management Area. This is the memory region holding > >> - * all the Interrupt Control Presenter (ICP) registers */ > >> - pnv_chip_icp_realize(chip, &error); > >> - if (error) { > >> - error_propagate(errp, error); > >> - return; > >> - } > >> - > >> - /* Processor Service Interface (PSI) Host Bridge */ > >> - object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip), > >> - "bar", &error_fatal); > >> - object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error); > >> - if (error) { > >> - error_propagate(errp, error); > >> - return; > >> - } > >> - pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs); > >> - > >> - /* Create the simplified OCC model */ > >> - object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error); > >> - if (error) { > >> - error_propagate(errp, error); > >> - return; > >> - } > >> - pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs); > >> + pcc->realize(chip, errp); > >> } > >> > >> static Property pnv_chip_properties[] = { > >> @@ -1003,26 +1031,29 @@ static void pnv_chip_class_init(ObjectClass *klass, void *data) > >> dc->desc = "PowerNV Chip"; > >> } > >> > >> -static ICSState *pnv_ics_get(XICSFabric *xi, int irq) > >> +static ICSState *pnv8_ics_get(XICSFabric *xi, int irq) > >> { > >> PnvMachineState *pnv = PNV_MACHINE(xi); > >> int i; > >> > >> for (i = 0; i < pnv->num_chips; i++) { > >> - if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) { > >> - return &pnv->chips[i]->psi.ics; > >> + Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); > >> + > >> + if (ics_valid_irq(&chip8->psi.ics, irq)) { > >> + return &chip8->psi.ics; > >> } > >> } > >> return NULL; > >> } > >> > >> -static void pnv_ics_resend(XICSFabric *xi) > >> +static void pnv8_ics_resend(XICSFabric *xi) > >> { > >> PnvMachineState *pnv = PNV_MACHINE(xi); > >> int i; > >> > >> for (i = 0; i < pnv->num_chips; i++) { > >> - ics_resend(&pnv->chips[i]->psi.ics); > >> + Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); > >> + ics_resend(&chip8->psi.ics); > >> } > >> } > >> > >> @@ -1042,15 +1073,14 @@ static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) > >> return NULL; > >> } > >> > >> -static ICPState *pnv_icp_get(XICSFabric *xi, int pir) > >> +static ICPState *pnv8_icp_get(XICSFabric *xi, int pir) > >> { > >> PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); > >> > >> return cpu ? ICP(cpu->intc) : NULL; > >> } > >> > >> -static void pnv_pic_print_info(InterruptStatsProvider *obj, > >> - Monitor *mon) > >> +static void pnv8_pic_print_info(InterruptStatsProvider *obj, Monitor *mon) > >> { > >> PnvMachineState *pnv = PNV_MACHINE(obj); > >> int i; > >> @@ -1063,7 +1093,8 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, > >> } > >> > >> for (i = 0; i < pnv->num_chips; i++) { > >> - ics_pic_print_info(&pnv->chips[i]->psi.ics, mon); > >> + Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); > >> + ics_pic_print_info(&chip8->psi.ics, mon); > >> } > >> } > >> > >> @@ -1098,7 +1129,7 @@ static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, > >> pnv->num_chips = num_chips; > >> } > >> > >> -static void pnv_machine_initfn(Object *obj) > >> +static void pnv_machine_instance_init(Object *obj) > >> { > >> PnvMachineState *pnv = PNV_MACHINE(obj); > >> pnv->num_chips = 1; > >> @@ -1117,8 +1148,6 @@ static void pnv_machine_class_props_init(ObjectClass *oc) > >> static void pnv_machine_class_init(ObjectClass *oc, void *data) > >> { > >> MachineClass *mc = MACHINE_CLASS(oc); > >> - XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); > >> - InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); > >> > >> mc->desc = "IBM PowerNV (Non-Virtualized)"; > >> mc->init = pnv_init; > >> @@ -1130,48 +1159,115 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) > >> mc->no_parallel = 1; > >> mc->default_boot_order = NULL; > >> mc->default_ram_size = 1 * G_BYTE; > >> - xic->icp_get = pnv_icp_get; > >> - xic->ics_get = pnv_ics_get; > >> - xic->ics_resend = pnv_ics_resend; > >> - ispc->print_info = pnv_pic_print_info; > >> > >> pnv_machine_class_props_init(oc); > >> } > >> > >> -#define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \ > >> - { \ > >> - .name = type, \ > >> - .class_init = class_initfn, \ > >> - .parent = TYPE_PNV_CHIP, \ > >> +static void pnv8_machine_class_init(ObjectClass *oc, void *data) > >> +{ > >> + MachineClass *mc = MACHINE_CLASS(oc); > >> + XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); > >> + InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); > >> + > >> + /* Power8 is the default */ > >> + mc->desc = "IBM PowerNV (Non-Virtualized) Power8"; > >> + mc->alias = "powernv"; > >> + mc->is_default = 1; > >> + > >> + xic->icp_get = pnv8_icp_get; > >> + xic->ics_get = pnv8_ics_get; > >> + xic->ics_resend = pnv8_ics_resend; > >> + ispc->print_info = pnv8_pic_print_info; > >> +} > >> + > >> +static void pnv9_machine_class_init(ObjectClass *oc, void *data) > >> +{ > >> + MachineClass *mc = MACHINE_CLASS(oc); > >> + > >> + mc->desc = "IBM PowerNV (Non-Virtualized) Power9"; > >> + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > >> +} > >> + > >> +#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ > >> + { \ > >> + .name = type, \ > >> + .class_init = class_initfn, \ > >> + .parent = TYPE_PNV8_CHIP, \ > >> + } > >> + > >> +#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ > >> + { \ > >> + .name = type, \ > >> + .class_init = class_initfn, \ > >> + .parent = TYPE_PNV9_CHIP, \ > >> } > >> > >> static const TypeInfo types[] = { > >> + /* > >> + * PowerNV machines and variants > >> + */ > >> { > >> .name = TYPE_PNV_MACHINE, > >> .parent = TYPE_MACHINE, > >> + .abstract = true, > >> .instance_size = sizeof(PnvMachineState), > >> - .instance_init = pnv_machine_initfn, > >> + .instance_init = pnv_machine_instance_init, > >> .class_init = pnv_machine_class_init, > >> .interfaces = (InterfaceInfo[]) { > >> - { TYPE_XICS_FABRIC }, > >> { TYPE_INTERRUPT_STATS_PROVIDER }, > >> { }, > >> }, > >> }, > >> { > >> + .name = MACHINE_TYPE_NAME("powernv9"), > >> + .parent = TYPE_PNV_MACHINE, > >> + .class_init = pnv9_machine_class_init, > >> + }, > >> + { > >> + .name = MACHINE_TYPE_NAME("powernv8"), > >> + .parent = TYPE_PNV_MACHINE, > >> + .class_init = pnv8_machine_class_init, > >> + .interfaces = (InterfaceInfo[]) { > >> + { TYPE_XICS_FABRIC }, > >> + { }, > >> + }, > >> + }, > >> + > >> + /* Power Chip */ > >> + { > >> .name = TYPE_PNV_CHIP, > >> .parent = TYPE_SYS_BUS_DEVICE, > >> .class_init = pnv_chip_class_init, > >> - .instance_init = pnv_chip_init, > >> + .instance_init = pnv_chip_instance_init, > >> .instance_size = sizeof(PnvChip), > >> .class_size = sizeof(PnvChipClass), > >> .abstract = true, > >> }, > >> - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), > >> - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), > >> - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), > >> - DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, > >> - pnv_chip_power8nvl_class_init), > >> + > >> + /* > >> + * P9 chips and variants > >> + */ > >> + { > >> + .name = TYPE_PNV9_CHIP, > >> + .parent = TYPE_PNV_CHIP, > >> + .instance_init = pnv_chip_power9_instance_init, > >> + .instance_size = sizeof(Pnv9Chip), > >> + }, > >> + DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), > >> + > >> + /* > >> + * P8 chips and variants > >> + */ > >> + { > >> + .name = TYPE_PNV8_CHIP, > >> + .parent = TYPE_PNV_CHIP, > >> + .instance_init = pnv_chip_power8_instance_init, > >> + .instance_size = sizeof(Pnv8Chip), > >> + }, > >> + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), > >> + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), > >> + DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, > >> + pnv_chip_power8nvl_class_init), > >> }; > >> > >> DEFINE_TYPES(types) > > > -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson