[PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency

[Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>]

From: Rex Zhu <Rex.Zhu@amd.com>

Display component can get tru max_displ_clk_in_khz instand of hardcode

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index c2576b235c52..35fe97a7bc24 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -251,13 +251,12 @@ static void pp_to_dc_clock_levels_with_voltage(
 	} else
 		clk_level_info->num_levels = pp_clks->num_levels;
 
-	DRM_INFO("DM_PPLIB: values for %s clock\n",
+	DRM_DEBUG("DM_PPLIB: values for %s clock\n",
 			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
 	for (i = 0; i < clk_level_info->num_levels; i++) {
-		DRM_INFO("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
-		/* translate 10kHz to kHz */
-		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
+		DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
+		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
 		clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
 	}
 }
@@ -364,15 +363,18 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
 {
 	struct amdgpu_device *adev = ctx->driver_context;
 	void *pp_handle = adev->powerplay.pp_handle;
-	struct pp_clock_levels_with_voltage pp_clk_info = {0};
+	struct pp_clock_levels_with_voltage pp_clks = { 0 };
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 
+	if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)
+		return false;
+
 	if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
 						     dc_to_pp_clock_type(clk_type),
-						     &pp_clk_info))
+						     &pp_clks))
 		return false;
 
-	pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
+	pp_to_dc_clock_levels_with_voltage(&pp_clks, clk_level_info, clk_type);
 
 	return true;
 }
-- 
2.17.1

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