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From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 3/4] ppc/pnv: introduce Pnv8Chip and Pnv9Chip models
Date: Mon, 25 Jun 2018 16:36:51 +1000	[thread overview]
Message-ID: <20180625063651.GE22971@umbus.fritz.box> (raw)
In-Reply-To: <36801260-2573-ce87-7f10-a6c76072ad23@kaod.org>

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On Wed, Jun 20, 2018 at 07:29:37AM +0200, Cédric Le Goater wrote:
> On 06/20/2018 02:56 AM, David Gibson wrote:
> > On Tue, Jun 19, 2018 at 07:24:44AM +0200, Cédric Le Goater wrote:
> >>
> >>>>>  typedef struct PnvChipClass {
> >>>>>      /*< private >*/
> >>>>> @@ -75,6 +95,7 @@ typedef struct PnvChipClass {
> >>>>>  
> >>>>>      hwaddr       xscom_base;
> >>>>>  
> >>>>> +    void (*realize)(PnvChip *chip, Error **errp);
> >>>>
> >>>> This looks the wrong way round from how things are usually done.
> >>>> Rather than having the base class realize() call the subclass specific
> >>>> realize hook, it's more usual for the subclass to set the
> >>>> dc->realize() and have it call a k->parent_realize() to call up the
> >>>> chain.  grep for device_class_set_parent_realize() for some more
> >>>> examples.
> >>>
> >>> Ah. That is more to my liking. There are a couple of models following
> >>> the wrong object pattern, xics, vio. I will check them.
> >>
> >> So XICS is causing some head-aches because the ics-kvm model inherits
> >> from ics-simple which inherits from ics-base. so we have a grand-parent
> >> class to handle.
> > 
> > Ok.  I mean, we should probably switch ics around to use the
> > parent_realize model, rather than the backwards one it does now.  But
> > it's not immediately obvious to me why having a grandparent class
> > breaks things.
> 
> If you follow the common realize pattern, you end up with a recursive 
> loop with one of the realize routine. I didn't dig much the issue.

Hmm.

> >> if we could affiliate ics-kvm directly to ics-base it would make the 
> >> family affair easier. we need to check migration though.
> > 
> > But that said, I've been thinking for a while that it might make sense
> > to fold ics-kvm into ics-base.  It seems very risky to have two
> > different object classes that are supposed to have guest-identical
> > behaviour.  Certainly adding any migratable state to one not the other
> > would be horribly wrong.
> 
> yes. clearly. something like bellow would be better:
> 
>                    +---------------+
>                    |     ICS       |
>          +---------+  common/base  +--------+
>          |         +---------------+        |
>          |                                  |
>          | spapr                    spapr   |
>          |  pnv                             |
>   +------v--------+                +--------v--------+
>   |     ICS       |                |       ICS       |
>   |  simple/QEMU  |                |       KVM       |
>   +---------------+                +-----------------+
> 
> with only some reset and realize handling in the subclasses. The only
> extra field we could add under the KVM class is the KVM XICS device fd.  

I think that would be an improvement over what we have, yes.  However,
it's not what I actually had in mind.  In fact I was planning on
getting rid of the KVM specific subclass entirely and merging it into
the base/simple classes with explicit if (kvm) logic.

The reason is that having different object classes for devices based
on accelerator is unusual and kind of dangerous.  We get away with it
because we don't have any migration information that gets tied to the
object class name - but that's a pretty non-obvious restriction that
would be easy to break in future.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2018-06-25  6:40 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-15 15:25 [Qemu-devel] [PATCH v2 0/4] ppc/pnv: new Pnv8Chip and Pnv9Chip models Cédric Le Goater
2018-06-15 15:25 ` [Qemu-devel] [PATCH v2 1/4] ppc/pnv: introduce a new intc_create() operation to the chip model Cédric Le Goater
2018-06-18  4:03   ` David Gibson
2018-06-15 15:25 ` [Qemu-devel] [PATCH v2 2/4] ppc/pnv: introduce a new isa_create() " Cédric Le Goater
2018-06-18  4:05   ` David Gibson
2018-06-15 15:25 ` [Qemu-devel] [PATCH v2 3/4] ppc/pnv: introduce Pnv8Chip and Pnv9Chip models Cédric Le Goater
2018-06-18 10:38   ` David Gibson
2018-06-18 11:30     ` Cédric Le Goater
2018-06-18 12:13       ` David Gibson
2018-06-19  5:24         ` Cédric Le Goater
2018-06-20  0:56           ` David Gibson
2018-06-20  5:29             ` Cédric Le Goater
2018-06-25  6:36               ` David Gibson [this message]
2018-06-25  7:14                 ` Cédric Le Goater
2018-06-15 15:25 ` [Qemu-devel] [PATCH v2 4/4] ppc/pnv: consolidate the creation of the ISA bus device tree Cédric Le Goater

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