[MODERATED] Re: [PATCH 8/8] L1TFv8 6

[Andi Kleen <ak@linux.intel.com>]

On Mon, Jun 25, 2018 at 09:04:34AM +0200, speck for Vlastimil Babka wrote:
> On 06/22/2018 06:56 PM, speck for Andi Kleen wrote:
> >> Because the macro machinery doesn't expect the arch-dependent swap entry
> >> format to be 32bit and pte to be 64bit, the results is even more macros,
> >> sorry about that.
> > 
> > Seems ugly and complicated. Perhaps it's better to just sacrifice the three bits.
> > Doubt anyone will really need it anyways, especially not on 32bit systems.
> 
> What three bits? You seem to be confusing this with my previous fix for
> 64bit max swap size, but this is something quite different.

You're right.

> 
> Before this patch, PAE code did not flip the offset bits, and was using
> the high pte word. That means bits 32-36 for type, 37-63 for offset.
> Lower word was zeroed, thus systems with 4GB or less memory should be
> safe, for 4GB to 128GB the swap type controls the "vulnerable" memory
> locations, above that also the offset. Is it correct that 32bit PAE HW
> phys limit is 64GB, but in the virtualized 32bit-pae guest on 64bit HW
> (that you were concerned about) that limit doesn't apply?

AFAIK it never applies on modern systems.

> 
> Now if we put the swap entry to the lower word starting with bit 9 (like
> 64bit), with 5 bits type we have 18 bits left for swap offset. That's
> just one 1GB. In the high word we have bits to avoid for L1TF (40 to 51
> at least?) so that's even worse. IMHO we have to use the whole 64bit
> entry then, which is what the patch does.

Ok.

-Andi