From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 28 Jun 2018 22:23:56 -0000 Received: from mga01.intel.com ([192.55.52.88]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fYfKV-0006p2-69 for speck@linutronix.de; Fri, 29 Jun 2018 00:23:55 +0200 Date: Thu, 28 Jun 2018 15:23:53 -0700 From: "Luck, Tony" Subject: [MODERATED] Re: [patch V4 13/13] x86/apic: Ignore secondary threads if nosmt=force Message-ID: <20180628222352.GA902@agluck-desk> References: <20180620201907.304694346@linutronix.de> <20180620201933.588840902@linutronix.de> <9a4cea33-05a7-b6d9-7f49-692603bd047f@linux.intel.com> MIME-Version: 1.0 In-Reply-To: <9a4cea33-05a7-b6d9-7f49-692603bd047f@linux.intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Thu, Jun 28, 2018 at 03:13:11PM -0700, speck for Dave Hansen wrote: > On 06/20/2018 01:19 PM, speck for Thomas Gleixner wrote: > > + /* > > + * If SMT is force disabled and the APIC ID belongs to > > + * a secondary thread, ignore it. > > + */ > > + if (apic_id_disabled(apicid)) { > > + pr_info_once("Ignoring secondary SMT threads\n"); > > + return -EINVAL; > > + } > > Thomas, this boottime-disable stuff just ends up ignoring the > hyperthread and leaves it alone, right? > > Some Intel folks pointed out a few problems with this. One is with > machine checks. If one thread is booted and has CR4.MCE=1, but the > other never gets booted and still has CR4.MCE=0, things go boom > (everything goes to shutdown state) if a machine check happens. There is also a power consumption concern. Asking BIOS folks now whether a logical CPU in the BIOS waiting for SIPI is in a deep C-state. -Tony