[DPU PATCH 3/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

[Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>]

Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 182 +++++++++++++++++++++++++++
 1 file changed, 182 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index cdaabeb3c995..537269636b43 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -221,6 +221,188 @@
 			#interrupt-cells = <2>;
 		};
 
+		mdss: mdss@ae00000 {
+			compatible = "qcom,dpu-mdss";
+			reg = <0xae00000 0x1000>;
+			reg-names = "mdss_phys";
+
+			power-domains = <&clock_dispcc 0>;
+
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&gcc GCC_DISP_AXI_CLK>,
+				 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+			clock-names = "iface_clk", "bus_clk", "core_clk";
+			clock-frequency = <0 0 300000000>;
+
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			iommus = <&apps_iommu 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mdss_mdp: mdp@ae01000 {
+				compatible = "qcom,dpu";
+				reg = <0x0ae01000 0x8f000>,
+				      <0x0aeb0000 0x2008>;
+				reg-names = "mdp_phys", "vbif_phys";
+
+				clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "iface_clk", "bus_clk", "core_clk", "vsync_clk";
+				clock-frequency = <0 0 300000000 19200000>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dpu_intf1_out: endpoint {
+							remote-endpoint = <&dsi0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dpu_intf2_out: endpoint {
+							remote-endpoint = <&dsi1_in>;
+						};
+					};
+				};
+			};
+
+			dsi0: dsi@ae94000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xae94000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4 0>;
+
+				clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte_clk",
+					      "byte_intf_clk",
+					      "pixel_clk",
+					      "core_clk",
+					      "iface_clk",
+					      "bus_clk";
+
+				phys = <&dsi0_phy>;
+				phy-names = "dsi-phy";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi0_in: endpoint {
+							remote-endpoint = <&dpu_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi0_phy: dsi-phy@ae94400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0xae94400 0x200>,
+				      <0xae94a00 0x1e0>,
+				      <0xae94600 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_pll",
+					    "dsi_phy_lane";
+
+				#clock-cells = <1>;
+
+				clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "iface_clk";
+			};
+
+			dsi1: dsi@ae96000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xae96000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <5 0>;
+
+				clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte_clk",
+					      "byte_intf_clk",
+					      "pixel_clk",
+					      "core_clk",
+					      "iface_clk",
+					      "bus_clk";
+
+				phys = <&dsi1_phy>;
+				phy-names = "dsi-phy";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi1_in: endpoint {
+							remote-endpoint = <&dpu_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi1_phy: dsi-phy@ae96400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0xae96400 0x200>,
+				      <0xae96a00 0x10e>,
+				      <0xae96600 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_pll",
+					    "dsi_phy_lane";
+
+				#clock-cells = <1>;
+
+				clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "iface_clk";
+			};
+		};
+
 		spmi_bus: spmi@c440000 {
 			compatible = "qcom,spmi-pmic-arb";
 			reg = <0xc440000 0x1100>,
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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