From mboxrd@z Thu Jan 1 00:00:00 1970 From: Oleksij Rempel Subject: [PATCH v7 2/6] dt-bindings: arm: fsl: add mu binding doc Date: Thu, 26 Jul 2018 08:53:27 +0200 Message-ID: <20180726065331.6186-3-o.rempel@pengutronix.de> References: <20180726065331.6186-1-o.rempel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180726065331.6186-1-o.rempel@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Shawn Guo , Fabio Estevam , Rob Herring , Mark Rutland , "A.s. Dong" , Vladimir Zapolskiy , Jassi Brar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sascha Hauer , dl-linux-imx List-Id: devicetree@vger.kernel.org From: Dong Aisheng The Messaging Unit module enables two processors within the SoC to communicate and coordinate by passing messages (e.g. data, status and control) through the MU interface. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Mark Rutland Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng --- .../devicetree/bindings/mailbox/fsl,mu.txt | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/fsl,mu.txt diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt new file mode 100644 index 000000000000..90e4905dfc69 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -0,0 +1,34 @@ +NXP i.MX Messaging Unit (MU) +-------------------------------------------------------------------- + +The Messaging Unit module enables two processors within the SoC to +communicate and coordinate by passing messages (e.g. data, status +and control) through the MU interface. The MU also provides the ability +for one processor to signal the other processor using interrupts. + +Because the MU manages the messaging between processors, the MU uses +different clocks (from each side of the different peripheral buses). +Therefore, the MU must synchronize the accesses from one side to the +other. The MU accomplishes synchronization using two sets of matching +registers (Processor A-facing, Processor B-facing). + +Messaging Unit Device Node: +============================= + +Required properties: +------------------- +- compatible : should be "fsl,-mu", the supported chips include + imx8qxp, imx8qm. +- reg : Should contain the registers location and length +- interrupts : Interrupt number. The interrupt specifier format depends + on the interrupt controller parent. +- #mbox-cells: Must be 0. Number of cells in a mailbox + +Examples: +-------- +lsio_mu0: mailbox@5d1b0000 { + compatible = "fsl,imx8qxp-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <0>; +}; -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: o.rempel@pengutronix.de (Oleksij Rempel) Date: Thu, 26 Jul 2018 08:53:27 +0200 Subject: [PATCH v7 2/6] dt-bindings: arm: fsl: add mu binding doc In-Reply-To: <20180726065331.6186-1-o.rempel@pengutronix.de> References: <20180726065331.6186-1-o.rempel@pengutronix.de> Message-ID: <20180726065331.6186-3-o.rempel@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Dong Aisheng The Messaging Unit module enables two processors within the SoC to communicate and coordinate by passing messages (e.g. data, status and control) through the MU interface. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Mark Rutland Cc: devicetree at vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng --- .../devicetree/bindings/mailbox/fsl,mu.txt | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/fsl,mu.txt diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt new file mode 100644 index 000000000000..90e4905dfc69 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -0,0 +1,34 @@ +NXP i.MX Messaging Unit (MU) +-------------------------------------------------------------------- + +The Messaging Unit module enables two processors within the SoC to +communicate and coordinate by passing messages (e.g. data, status +and control) through the MU interface. The MU also provides the ability +for one processor to signal the other processor using interrupts. + +Because the MU manages the messaging between processors, the MU uses +different clocks (from each side of the different peripheral buses). +Therefore, the MU must synchronize the accesses from one side to the +other. The MU accomplishes synchronization using two sets of matching +registers (Processor A-facing, Processor B-facing). + +Messaging Unit Device Node: +============================= + +Required properties: +------------------- +- compatible : should be "fsl,-mu", the supported chips include + imx8qxp, imx8qm. +- reg : Should contain the registers location and length +- interrupts : Interrupt number. The interrupt specifier format depends + on the interrupt controller parent. +- #mbox-cells: Must be 0. Number of cells in a mailbox + +Examples: +-------- +lsio_mu0: mailbox at 5d1b0000 { + compatible = "fsl,imx8qxp-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <0>; +}; -- 2.18.0