From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Mark Brown <broonie@kernel.org>, James Hogan <jhogan@kernel.org>
Cc: Paul Burton <paul.burton@mips.com>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mips@linux-mips.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Allan Nielsen <allan.nielsen@microsemi.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: [PATCH v2 0/4] Add support for MSCC Ocelot SPI
Date: Fri, 27 Jul 2018 14:05:31 +0200 [thread overview]
Message-ID: <20180727120535.16504-1-alexandre.belloni@bootlin.com> (raw)
Hello,
The MSCC MIPS SoC line uses a designware IP for the SPI controller but
still requires some special handling to give control of the SPI
interface to the IP and also has a specific handling for the chip
select.
Changes in v2:
- Removed already applied patches
- separated DT binding changes from the driver patch
Alexandre Belloni (4):
dt-bindings: spi: snps,dw-apb-ssi: document Microsemi integration
spi: dw-mmio: add MSCC Ocelot support
mips: dts: mscc: Add spi on Ocelot
mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123
arch/mips/boot/dts/mscc/ocelot.dtsi | 11 +++
arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 10 +++
drivers/spi/spi-dw-mmio.c | 91 +++++++++++++++++++++++
3 files changed, 112 insertions(+)
--
2.18.0
next reply other threads:[~2018-07-27 12:05 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-27 12:05 Alexandre Belloni [this message]
2018-07-27 12:05 ` [PATCH v2 1/4] dt-bindings: spi: snps,dw-apb-ssi: document Microsemi integration Alexandre Belloni
2018-07-27 12:05 ` [PATCH v2 2/4] spi: dw-mmio: add MSCC Ocelot support Alexandre Belloni
2018-07-27 13:07 ` Andy Shevchenko
2018-07-27 15:26 ` Alexandre Belloni
2018-07-27 12:05 ` [PATCH v2 3/4] mips: dts: mscc: Add spi on Ocelot Alexandre Belloni
2018-07-27 12:05 ` [PATCH v2 4/4] mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123 Alexandre Belloni
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