From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D96BAC6778F for ; Fri, 27 Jul 2018 11:34:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A9BC2089F for ; Fri, 27 Jul 2018 11:34:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=bidouilliste.com header.i=@bidouilliste.com header.b="lBYa2NwO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7A9BC2089F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bidouilliste.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731039AbeG0M4M (ORCPT ); Fri, 27 Jul 2018 08:56:12 -0400 Received: from mail.blih.net ([212.83.177.182]:61474 "EHLO mail.blih.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730425AbeG0M4M (ORCPT ); Fri, 27 Jul 2018 08:56:12 -0400 Received: from mail.blih.net (mail.blih.net [212.83.177.182]) by mail.blih.net (OpenSMTPD) with ESMTP id 53f71e28; Fri, 27 Jul 2018 13:34:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=bidouilliste.com; h=date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=mail; bh=9vP1Dlcu3RCVipRmSaeg+cn4e7s=; b=lBYa2NwOSGg5MExpJ99rykF8TfB5 ytQxDT5sjCEcQyBnQ3J/kzEd5+/QNcWX9o9qCO+c5Cmv8eeoF+gjxEikE3PxHxwL m3IRijPCcaDxffUoT3QZaz1v/lO8KqXRxFHCm0V2Kg8uXpH2IXL0F+Fs/W4c3hv9 K88MsSM+7i846tU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=bidouilliste.com; h=date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; q=dns; s= mail; b=MYHCVUpfKX+WFLkDh1uiyW6TgzmTvaMuuVDjvQoy0s0BWn7X8ZNqzw/F yBQrmkgcVcDA1RiYMSHe0wfuadCwZcGbPA7e9C2y72rzN7m5IqYwGLFXTTN7YhHA W+5xTJZsT9wC7HNIMs/cN8d4Lpx4QQMN7yrIyqIifLMX05m0sRM= Received: from skull.home.blih.net (ip-9.net-89-3-105.rev.numericable.fr [89.3.105.9]) by mail.blih.net (OpenSMTPD) with ESMTPSA id 0c26672f TLS version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO; Fri, 27 Jul 2018 13:34:39 +0200 (CEST) Date: Fri, 27 Jul 2018 13:34:39 +0200 From: Emmanuel Vadot To: Emmanuel Vadot Cc: Maxime Ripard , mark.rutland@arm.com, devicetree@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, Emmanuel Vadot , wens@csie.org, robh+dt@kernel.org, srinivas.kandagatla@linaro.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 5/5] arm64: dts: allwinner: h5: Add SID for H5 Message-Id: <20180727133439.2f54a1a06d7a80560027cda3@bidouilliste.com> In-Reply-To: <20180727125654.ec813df71b492201aea2ca5f@bidouilliste.com> References: <20180724101522.68165-1-manu@freebsd.org> <20180724101522.68165-5-manu@freebsd.org> <20180724130004.ynaiabshexrrbvo4@flea> <20180724153432.e398bddfe63e51e8dcebfc46@bidouilliste.com> <20180724144218.jdvgrcqkz2kmohqx@flea> <20180724165501.d8f01bf20c7cc43e7ed7fc62@bidouilliste.com> <20180726115409.7hqtvx4rdqcqdjrq@flea> <20180727125654.ec813df71b492201aea2ca5f@bidouilliste.com> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; amd64-portbld-freebsd12.0) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 27 Jul 2018 12:56:54 +0200 Emmanuel Vadot wrote: > On Thu, 26 Jul 2018 13:54:09 +0200 > Maxime Ripard wrote: > > > On Tue, Jul 24, 2018 at 04:55:01PM +0200, Emmanuel Vadot wrote: > > > On Tue, 24 Jul 2018 16:42:18 +0200 > > > Maxime Ripard wrote: > > > > > > > On Tue, Jul 24, 2018 at 03:34:32PM +0200, Emmanuel Vadot wrote: > > > > > On Tue, 24 Jul 2018 15:00:04 +0200 > > > > > Maxime Ripard wrote: > > > > > > > > > > > On Tue, Jul 24, 2018 at 12:15:22PM +0200, Emmanuel Vadot wrote: > > > > > > > The SID controller on H5 look the same as the one present in the A64. > > > > > > > But in case we find some difference one day at a compatible string > > > > > > > of it's own and a fallback to the A64 one. > > > > > > > > > > > > > > Signed-off-by: Emmanuel Vadot > > > > > > > --- > > > > > > > arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 5 +++++ > > > > > > > 1 file changed, 5 insertions(+) > > > > > > > > > > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > > > > > > > index 62d646baac3c..28183bf77164 100644 > > > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > > > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > > > > > > > @@ -129,3 +129,8 @@ > > > > > > > ; > > > > > > > compatible = "allwinner,sun50i-h5-pinctrl"; > > > > > > > }; > > > > > > > + > > > > > > > +&sid { > > > > > > > + compatible = "allwinner,sun50i-h5-sid", > > > > > > > + "allwinner,sun50i-a64-sid"; > > > > > > > +}; > > > > > > > > > > > > This is still a bit pointless, please remove the common node. > > > > > > > > > > You mean directly declare sid controller in the SoC dtsi and not > > > > > have a common node in sunxi-h3-h5.dtsi ? > > > > > > > > Yep > > > > > > The reason I've put it in the common file is because I'll send patches > > > for the nvmem-cells needed for thermal, and those are common between > > > the two. Other nvmem-cells are also common (like the chipid and > > > probably other). > > > > Then we'll see what we can have in common and what not when we'll have > > something in common? > > Will it make more sense that I just send a new series with nvmem-cells > now along with thermal bindings ? My bad, I remembered H5 thermal sensor being the same as H3 but I was wrong. I'll send a v3 with your changes suggestion and we'll see later for thermal sensor. > > Maxime > > > > -- > > Maxime Ripard, Bootlin (formerly Free Electrons) > > Embedded Linux and Kernel engineering > > https://bootlin.com > > > -- > Emmanuel Vadot > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Emmanuel Vadot From mboxrd@z Thu Jan 1 00:00:00 1970 From: manu@bidouilliste.com (Emmanuel Vadot) Date: Fri, 27 Jul 2018 13:34:39 +0200 Subject: [PATCH v2 5/5] arm64: dts: allwinner: h5: Add SID for H5 In-Reply-To: <20180727125654.ec813df71b492201aea2ca5f@bidouilliste.com> References: <20180724101522.68165-1-manu@freebsd.org> <20180724101522.68165-5-manu@freebsd.org> <20180724130004.ynaiabshexrrbvo4@flea> <20180724153432.e398bddfe63e51e8dcebfc46@bidouilliste.com> <20180724144218.jdvgrcqkz2kmohqx@flea> <20180724165501.d8f01bf20c7cc43e7ed7fc62@bidouilliste.com> <20180726115409.7hqtvx4rdqcqdjrq@flea> <20180727125654.ec813df71b492201aea2ca5f@bidouilliste.com> Message-ID: <20180727133439.2f54a1a06d7a80560027cda3@bidouilliste.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 27 Jul 2018 12:56:54 +0200 Emmanuel Vadot wrote: > On Thu, 26 Jul 2018 13:54:09 +0200 > Maxime Ripard wrote: > > > On Tue, Jul 24, 2018 at 04:55:01PM +0200, Emmanuel Vadot wrote: > > > On Tue, 24 Jul 2018 16:42:18 +0200 > > > Maxime Ripard wrote: > > > > > > > On Tue, Jul 24, 2018 at 03:34:32PM +0200, Emmanuel Vadot wrote: > > > > > On Tue, 24 Jul 2018 15:00:04 +0200 > > > > > Maxime Ripard wrote: > > > > > > > > > > > On Tue, Jul 24, 2018 at 12:15:22PM +0200, Emmanuel Vadot wrote: > > > > > > > The SID controller on H5 look the same as the one present in the A64. > > > > > > > But in case we find some difference one day at a compatible string > > > > > > > of it's own and a fallback to the A64 one. > > > > > > > > > > > > > > Signed-off-by: Emmanuel Vadot > > > > > > > --- > > > > > > > arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 5 +++++ > > > > > > > 1 file changed, 5 insertions(+) > > > > > > > > > > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > > > > > > > index 62d646baac3c..28183bf77164 100644 > > > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > > > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > > > > > > > @@ -129,3 +129,8 @@ > > > > > > > ; > > > > > > > compatible = "allwinner,sun50i-h5-pinctrl"; > > > > > > > }; > > > > > > > + > > > > > > > +&sid { > > > > > > > + compatible = "allwinner,sun50i-h5-sid", > > > > > > > + "allwinner,sun50i-a64-sid"; > > > > > > > +}; > > > > > > > > > > > > This is still a bit pointless, please remove the common node. > > > > > > > > > > You mean directly declare sid controller in the SoC dtsi and not > > > > > have a common node in sunxi-h3-h5.dtsi ? > > > > > > > > Yep > > > > > > The reason I've put it in the common file is because I'll send patches > > > for the nvmem-cells needed for thermal, and those are common between > > > the two. Other nvmem-cells are also common (like the chipid and > > > probably other). > > > > Then we'll see what we can have in common and what not when we'll have > > something in common? > > Will it make more sense that I just send a new series with nvmem-cells > now along with thermal bindings ? My bad, I remembered H5 thermal sensor being the same as H3 but I was wrong. I'll send a v3 with your changes suggestion and we'll see later for thermal sensor. > > Maxime > > > > -- > > Maxime Ripard, Bootlin (formerly Free Electrons) > > Embedded Linux and Kernel engineering > > https://bootlin.com > > > -- > Emmanuel Vadot > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Emmanuel Vadot