[PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Mika Kuoppala]

The register for 0xe420 is unable to hold any value, including
this bit. The documentation is also mixed between having a
register bit for toggle and having a state command setup
for it. Apparently the register toggle is deprecated.

Remove the register toggle as evidence shows it's futile.

The thing remaining is an apology and humble request for
Mesa folks to resurrect their state setup for this as they
were on right track from start.

This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.

Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")
References: HSDES#1406393558
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 ---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7bdc214ffb6e..e0f5999fff07 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2859,9 +2859,6 @@ enum i915_power_well_id {
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)
 
-#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
-#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
-
 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT			16
 #define   GEN6_BLITTER_FBC_NOTIFY			(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index f8bb32e974f6..4bcdeaf8d98f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -508,9 +508,6 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
-	/* WaEnableFloatBlendOptimization:icl */
-	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
-
 	return 0;
 }
 
-- 
2.17.1

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Re: [PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Chris Wilson]

Quoting Mika Kuoppala (2018-07-30 13:06:36)
> The register for 0xe420 is unable to hold any value, including
> this bit. The documentation is also mixed between having a
> register bit for toggle and having a state command setup
> for it. Apparently the register toggle is deprecated.
> 
> Remove the register toggle as evidence shows it's futile.
> 
> The thing remaining is an apology and humble request for
> Mesa folks to resurrect their state setup for this as they
> were on right track from start.
> 
> This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.
> 
> Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")
> References: HSDES#1406393558
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Anuj Phogat <anuj.phogat@gmail.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>

The test results do confirm the register is a red herring, but we need
someone to confirm that we aren't just using the wrong register etc.
-Chris
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✓ Fi.CI.BAT: success for Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/icl: WaEnableFloatBlendOptimization"
URL   : https://patchwork.freedesktop.org/series/47422/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4594 -> Patchwork_9807 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47422/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9807 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries:
      {fi-icl-u}:         NOTRUN -> DMESG-WARN (fdo#107396)

    igt@drv_selftest@live_hangcheck:
      fi-kbl-guc:         PASS -> DMESG-FAIL (fdo#106947)
      {fi-icl-u}:         NOTRUN -> INCOMPLETE (fdo#107399)

    igt@drv_selftest@live_objects:
      {fi-icl-u}:         NOTRUN -> DMESG-FAIL (fdo#107398)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       PASS -> DMESG-WARN (fdo#107139, fdo#105128)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         PASS -> INCOMPLETE (fdo#103927)
      {fi-icl-u}:         NOTRUN -> DMESG-WARN (fdo#107382) +4

    {igt@kms_psr@primary_mmap_gtt}:
      fi-cnl-psr:         PASS -> DMESG-WARN (fdo#107372)

    {igt@kms_psr@primary_page_flip}:
      {fi-icl-u}:         NOTRUN -> FAIL (fdo#107383) +3

    
    ==== Possible fixes ====

    igt@drv_selftest@live_coherency:
      fi-gdg-551:         DMESG-FAIL (fdo#107164) -> PASS

    igt@kms_chamelium@hdmi-edid-read:
      fi-kbl-7500u:       FAIL (fdo#103841) -> SKIP

    igt@kms_chamelium@hdmi-hpd-fast:
      fi-kbl-7500u:       FAIL (fdo#102672, fdo#103841) -> SKIP

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
  fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
  fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
  fdo#107382 https://bugs.freedesktop.org/show_bug.cgi?id=107382
  fdo#107383 https://bugs.freedesktop.org/show_bug.cgi?id=107383
  fdo#107396 https://bugs.freedesktop.org/show_bug.cgi?id=107396
  fdo#107398 https://bugs.freedesktop.org/show_bug.cgi?id=107398
  fdo#107399 https://bugs.freedesktop.org/show_bug.cgi?id=107399


== Participating hosts (51 -> 47) ==

  Additional (2): fi-icl-u fi-kbl-8809g 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


== Build changes ==

    * Linux: CI_DRM_4594 -> Patchwork_9807

  CI_DRM_4594: bebee8b5e1691b4b0a356a9b6443f9793e7f15d9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9807: 284341d472b275e9841e69a5f4898eee6f367458 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

284341d472b2 Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9807/issues.html
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Re: ✓ Fi.CI.BAT: success for Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Chris Wilson]

Quoting Patchwork (2018-07-30 14:23:46)
> == Participating hosts (51 -> 47) ==
> 
>   Additional (2): fi-icl-u fi-kbl-8809g 

So checking the fi-icl-u results does indeed confirm that
live_workarounds is fixed.
-Chris
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Re: ✓ Fi.CI.BAT: success for Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Patchwork (2018-07-30 14:23:46)
>> == Participating hosts (51 -> 47) ==
>> 
>>   Additional (2): fi-icl-u fi-kbl-8809g 
>
> So checking the fi-icl-u results does indeed confirm that
> live_workarounds is fixed.

Hmm, gem_workarounds is fixed?

I looked at live_workarounds and it seems to check
the validity of the whitelists (across resets etc).

-Mika
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Re: ✓ Fi.CI.BAT: success for Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Chris Wilson]

Quoting Mika Kuoppala (2018-07-30 14:59:01)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > Quoting Patchwork (2018-07-30 14:23:46)
> >> == Participating hosts (51 -> 47) ==
> >> 
> >>   Additional (2): fi-icl-u fi-kbl-8809g 
> >
> > So checking the fi-icl-u results does indeed confirm that
> > live_workarounds is fixed.
> 
> Hmm, gem_workarounds is fixed?
> 
> I looked at live_workarounds and it seems to check
> the validity of the whitelists (across resets etc).

icl hasn't survived long enough to complete a run with gem_workarounds
;) I was just looking at the live_hangcheck results for this series.
-Chris
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✓ Fi.CI.IGT: success for Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/icl: WaEnableFloatBlendOptimization"
URL   : https://patchwork.freedesktop.org/series/47422/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4594_full -> Patchwork_9807_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9807_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9807_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9807_full:

  === IGT changes ===

    ==== Warnings ====

    igt@kms_plane_lowres@pipe-a-tiling-none:
      shard-snb:          PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_9807_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@shrink:
      shard-glk:          PASS -> INCOMPLETE (k.org#198133, fdo#103359, fdo#106886)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#105363)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      shard-kbl:          DMESG-FAIL (fdo#106947, fdo#106560) -> PASS

    igt@gem_ctx_isolation@vcs0-s3:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-kbl:          INCOMPLETE (fdo#106023, fdo#103665) -> PASS

    igt@kms_flip@dpms-vs-vblank-race:
      shard-glk:          FAIL (fdo#103060) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    igt@kms_universal_plane@cursor-fb-leak-pipe-b:
      shard-apl:          FAIL (fdo#107241) -> PASS

    igt@perf@blocking:
      shard-hsw:          FAIL (fdo#102252) -> PASS

    
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#107241 https://bugs.freedesktop.org/show_bug.cgi?id=107241
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4594 -> Patchwork_9807

  CI_DRM_4594: bebee8b5e1691b4b0a356a9b6443f9793e7f15d9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4581: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9807: 284341d472b275e9841e69a5f4898eee6f367458 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9807/shards.html
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Re: [PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2018-07-30 13:06:36)
>> The register for 0xe420 is unable to hold any value, including
>> this bit. The documentation is also mixed between having a
>> register bit for toggle and having a state command setup
>> for it. Apparently the register toggle is deprecated.
>> 
>> Remove the register toggle as evidence shows it's futile.
>> 
>> The thing remaining is an apology and humble request for
>> Mesa folks to resurrect their state setup for this as they
>> were on right track from start.
>> 
>> This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.
>> 
>> Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")
>> References: HSDES#1406393558
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Anuj Phogat <anuj.phogat@gmail.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> The test results do confirm the register is a red herring, but we need
> someone to confirm that we aren't just using the wrong register etc.

I will ask around. Thanks for ack. Pushed.
-Mika
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Re: [PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Anuj Phogat]

[-- Attachment #1.1: Type: text/plain, Size: 2633 bytes --]

On Mon, Jul 30, 2018 at 5:07 AM Mika Kuoppala <mika.kuoppala@linux.intel.com>
wrote:

> The register for 0xe420 is unable to hold any value, including
> this bit. The documentation is also mixed between having a
> register bit for toggle and having a state command setup
> for it. Apparently the register toggle is deprecated.
>
>   CACHE_MODE_SS is not listed in
a
gfxspecs table
which lists all
user mode
  non-privileged registers. So,
do you think
making any changes
to the register
  from mesa will hold?

> Remove the register toggle as evidence shows it's futile.
>
> The thing remaining is an apology and humble request for
> Mesa folks to resurrect their state setup for this as they
> were on right track from start.
>
> This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.
>
> Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")
> References: HSDES#1406393558
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Anuj Phogat <anuj.phogat@gmail.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 3 ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 3 ---
>  2 files changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 7bdc214ffb6e..e0f5999fff07 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2859,9 +2859,6 @@ enum i915_power_well_id {
>  #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE    (1 << 6)
>  #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
>
> -#define GEN10_CACHE_MODE_SS                    _MMIO(0xe420)
> -#define   FLOAT_BLEND_OPTIMIZATION_ENABLE      (1 << 4)
> -
>  #define GEN6_BLITTER_ECOSKPD   _MMIO(0x221d0)
>  #define   GEN6_BLITTER_LOCK_SHIFT                      16
>  #define   GEN6_BLITTER_FBC_NOTIFY                      (1 << 3)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index f8bb32e974f6..4bcdeaf8d98f 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -508,9 +508,6 @@ static int icl_ctx_workarounds_init(struct
> drm_i915_private *dev_priv)
>                 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>                                   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>
> -       /* WaEnableFloatBlendOptimization:icl */
> -       WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS,
> FLOAT_BLEND_OPTIMIZATION_ENABLE);
> -
>         return 0;
>  }
>
> --
> 2.17.1
>
>

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Re: [PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Chris Wilson]

Quoting Anuj Phogat (2018-08-03 20:24:09)
> 
> 
> On Mon, Jul 30, 2018 at 5:07 AM Mika Kuoppala <mika.kuoppala@linux.intel.com>
> wrote:
> 
>     The register for 0xe420 is unable to hold any value, including
>     this bit. The documentation is also mixed between having a
>     register bit for toggle and having a state command setup
>     for it. Apparently the register toggle is deprecated.
> 
> 
>   CACHE_MODE_SS is not listed in
> a
> gfxspecs table 
> which lists all
> user mode
>   non-privileged registers. So,
> do you think
> making any changes
> to the register
>   from mesa will hold?

No, a privileged write to the register from inside the ring didn't
stick, so something is amiss.
-Chris
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Re: [PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Anuj Phogat]

[-- Attachment #1.1: Type: text/plain, Size: 1051 bytes --]

On Mon, Aug 6, 2018 at 9:14 AM Chris Wilson <chris@chris-wilson.co.uk>
wrote:

> Quoting Anuj Phogat (2018-08-03 20:24:09)
> >
> >
> > On Mon, Jul 30, 2018 at 5:07 AM Mika Kuoppala <
> mika.kuoppala@linux.intel.com>
> > wrote:
> >
> >     The register for 0xe420 is unable to hold any value, including
> >     this bit. The documentation is also mixed between having a
> >     register bit for toggle and having a state command setup
> >     for it. Apparently the register toggle is deprecated.
> >
> >
> >   CACHE_MODE_SS is not listed in
> > a
> > gfxspecs table
> > which lists all
> > user mode
> >   non-privileged registers. So,
> > do you think
> > making any changes
> > to the register
> >   from mesa will hold?
>
> No, a privileged write to the register from inside the ring didn't
> stick, so something is amiss.
>
ok. Mika's commit message confused me where he mentioned
about adding back the state
setup for this bit in mesa.
But, as
I understand now the changes won't stick in the register. So,
no changes required  in mesa.

-Chris
>

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