From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71ECAC43142 for ; Tue, 31 Jul 2018 11:27:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 17699208A3 for ; Tue, 31 Jul 2018 11:27:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 17699208A3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732085AbeGaNHh (ORCPT ); Tue, 31 Jul 2018 09:07:37 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:50662 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731639AbeGaNHg (ORCPT ); Tue, 31 Jul 2018 09:07:36 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 40D754021700; Tue, 31 Jul 2018 11:27:44 +0000 (UTC) Received: from prarit.bos.redhat.com (prarit-guest.khw.lab.eng.bos.redhat.com [10.16.186.145]) by smtp.corp.redhat.com (Postfix) with ESMTP id DA4A610C1F; Tue, 31 Jul 2018 11:27:43 +0000 (UTC) From: Prarit Bhargava To: bp@alien8.de Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, sironi@amazon.de, tony.luck@intel.com, Prarit Bhargava , stable@vger.kernel.org Subject: [PATCH v2] arch/x86: Fix boot_cpu_data.microcode version output Date: Tue, 31 Jul 2018 07:27:39 -0400 Message-Id: <20180731112739.32338-1-prarit@redhat.com> In-Reply-To: <20180601121939.GA23298@nazgul.tnic> References: <20180601121939.GA23298@nazgul.tnic> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Tue, 31 Jul 2018 11:27:44 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Tue, 31 Jul 2018 11:27:44 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'prarit@redhat.com' RCPT:'' Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org I tested this on AMD Ryzen & Intel Broadwell system and dumped the boot_cpu_data before and after a microcode update. On the Intel system I also did a fatal MCE using mce-inject to confirm the output from the mce handling code. P. ---8<--- On systems where a runtime microcode update has occurred the microcode version output in a MCE log record is wrong because boot_cpu_data.microcode is not updated during runtime. Update boot_cpu_data.microcode when the BSP's microcode is updated. Fixes: fa94d0c6e0f3 ("x86/MCE: Save microcode revision in machine check records") Suggested-by: Borislav Petkov Signed-off-by: Prarit Bhargava Cc: stable@vger.kernel.org Cc: sironi@amazon.de Cc: tony.luck@intel.com --- Changes in v2: Use mc_amd->hdr.patch_id on AMD arch/x86/kernel/cpu/microcode/amd.c | 4 ++++ arch/x86/kernel/cpu/microcode/intel.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 0624957aa068..63b072377ba4 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -537,6 +537,10 @@ static enum ucode_state apply_microcode_amd(int cpu) uci->cpu_sig.rev = mc_amd->hdr.patch_id; c->microcode = mc_amd->hdr.patch_id; + /* Update boot_cpu_data's revision too, if we're on the BSP: */ + if (c->cpu_index == boot_cpu_data.cpu_index) + boot_cpu_data.microcode = mc_amd->hdr.patch_id; + return UCODE_UPDATED; } diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 97ccf4c3b45b..256d336cbc04 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -851,6 +851,10 @@ static enum ucode_state apply_microcode_intel(int cpu) uci->cpu_sig.rev = rev; c->microcode = rev; + /* Update boot_cpu_data's revision too, if we're on the BSP: */ + if (c->cpu_index == boot_cpu_data.cpu_index) + boot_cpu_data.microcode = rev; + return UCODE_UPDATED; } -- 2.17.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v2] arch/x86: Fix boot_cpu_data.microcode version output From: Prarit Bhargava Message-Id: <20180731112739.32338-1-prarit@redhat.com> Date: Tue, 31 Jul 2018 07:27:39 -0400 To: bp@alien8.de Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, sironi@amazon.de, tony.luck@intel.com, Prarit Bhargava , stable@vger.kernel.org List-ID: SSB0ZXN0ZWQgdGhpcyBvbiBBTUQgUnl6ZW4gJiBJbnRlbCBCcm9hZHdlbGwgc3lzdGVtIGFuZCBk dW1wZWQgdGhlCmJvb3RfY3B1X2RhdGEgYmVmb3JlIGFuZCBhZnRlciBhIG1pY3JvY29kZSB1cGRh dGUuICBPbiB0aGUgSW50ZWwKc3lzdGVtIEkgYWxzbyBkaWQgYSBmYXRhbCBNQ0UgdXNpbmcgbWNl LWluamVjdCB0byBjb25maXJtIHRoZSBvdXRwdXQKZnJvbSB0aGUgbWNlIGhhbmRsaW5nIGNvZGUu CgpQLgoKLS0tODwtLS0KCk9uIHN5c3RlbXMgd2hlcmUgYSBydW50aW1lIG1pY3JvY29kZSB1cGRh dGUgaGFzIG9jY3VycmVkIHRoZSBtaWNyb2NvZGUKdmVyc2lvbiBvdXRwdXQgaW4gYSBNQ0UgbG9n IHJlY29yZCBpcyB3cm9uZyBiZWNhdXNlCmJvb3RfY3B1X2RhdGEubWljcm9jb2RlIGlzIG5vdCB1 cGRhdGVkIGR1cmluZyBydW50aW1lLgoKVXBkYXRlIGJvb3RfY3B1X2RhdGEubWljcm9jb2RlIHdo ZW4gdGhlIEJTUCdzIG1pY3JvY29kZSBpcyB1cGRhdGVkLgoKRml4ZXM6IGZhOTRkMGM2ZTBmMyAo Ing4Ni9NQ0U6IFNhdmUgbWljcm9jb2RlIHJldmlzaW9uIGluIG1hY2hpbmUgY2hlY2sgcmVjb3Jk cyIpClN1Z2dlc3RlZC1ieTogQm9yaXNsYXYgUGV0a292IDxicEBhbGllbjguY29tPgpTaWduZWQt b2ZmLWJ5OiBQcmFyaXQgQmhhcmdhdmEgPHByYXJpdEByZWRoYXQuY29tPgpDYzogc3RhYmxlQHZn ZXIua2VybmVsLm9yZwpDYzogc2lyb25pQGFtYXpvbi5kZQpDYzogdG9ueS5sdWNrQGludGVsLmNv bQotLS0KQ2hhbmdlcyBpbiB2MjogVXNlIG1jX2FtZC0+aGRyLnBhdGNoX2lkIG9uIEFNRAoKIGFy Y2gveDg2L2tlcm5lbC9jcHUvbWljcm9jb2RlL2FtZC5jICAgfCA0ICsrKysKIGFyY2gveDg2L2tl cm5lbC9jcHUvbWljcm9jb2RlL2ludGVsLmMgfCA0ICsrKysKIDIgZmlsZXMgY2hhbmdlZCwgOCBp bnNlcnRpb25zKCspCgpkaWZmIC0tZ2l0IGEvYXJjaC94ODYva2VybmVsL2NwdS9taWNyb2NvZGUv YW1kLmMgYi9hcmNoL3g4Ni9rZXJuZWwvY3B1L21pY3JvY29kZS9hbWQuYwppbmRleCAwNjI0OTU3 YWEwNjguLjYzYjA3MjM3N2JhNCAxMDA2NDQKLS0tIGEvYXJjaC94ODYva2VybmVsL2NwdS9taWNy b2NvZGUvYW1kLmMKKysrIGIvYXJjaC94ODYva2VybmVsL2NwdS9taWNyb2NvZGUvYW1kLmMKQEAg LTUzNyw2ICs1MzcsMTAgQEAgc3RhdGljIGVudW0gdWNvZGVfc3RhdGUgYXBwbHlfbWljcm9jb2Rl X2FtZChpbnQgY3B1KQogCXVjaS0+Y3B1X3NpZy5yZXYgPSBtY19hbWQtPmhkci5wYXRjaF9pZDsK IAljLT5taWNyb2NvZGUgPSBtY19hbWQtPmhkci5wYXRjaF9pZDsKIAorCS8qIFVwZGF0ZSBib290 X2NwdV9kYXRhJ3MgcmV2aXNpb24gdG9vLCBpZiB3ZSdyZSBvbiB0aGUgQlNQOiAqLworCWlmIChj LT5jcHVfaW5kZXggPT0gYm9vdF9jcHVfZGF0YS5jcHVfaW5kZXgpCisJCWJvb3RfY3B1X2RhdGEu bWljcm9jb2RlID0gIG1jX2FtZC0+aGRyLnBhdGNoX2lkOworCiAJcmV0dXJuIFVDT0RFX1VQREFU RUQ7CiB9CiAKZGlmZiAtLWdpdCBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWljcm9jb2RlL2ludGVs LmMgYi9hcmNoL3g4Ni9rZXJuZWwvY3B1L21pY3JvY29kZS9pbnRlbC5jCmluZGV4IDk3Y2NmNGMz YjQ1Yi4uMjU2ZDMzNmNiYzA0IDEwMDY0NAotLS0gYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L21pY3Jv Y29kZS9pbnRlbC5jCisrKyBiL2FyY2gveDg2L2tlcm5lbC9jcHUvbWljcm9jb2RlL2ludGVsLmMK QEAgLTg1MSw2ICs4NTEsMTAgQEAgc3RhdGljIGVudW0gdWNvZGVfc3RhdGUgYXBwbHlfbWljcm9j b2RlX2ludGVsKGludCBjcHUpCiAJdWNpLT5jcHVfc2lnLnJldiA9IHJldjsKIAljLT5taWNyb2Nv ZGUgPSByZXY7CiAKKwkvKiBVcGRhdGUgYm9vdF9jcHVfZGF0YSdzIHJldmlzaW9uIHRvbywgaWYg d2UncmUgb24gdGhlIEJTUDogKi8KKwlpZiAoYy0+Y3B1X2luZGV4ID09IGJvb3RfY3B1X2RhdGEu Y3B1X2luZGV4KQorCQlib290X2NwdV9kYXRhLm1pY3JvY29kZSA9IHJldjsKKwogCXJldHVybiBV Q09ERV9VUERBVEVEOwogfQogCg==