From mboxrd@z Thu Jan 1 00:00:00 1970 From: Oleksij Rempel Subject: [PATCH v8 2/4] dt-bindings: mailbox: imx-mu: add generic MU channel support Date: Tue, 31 Jul 2018 16:11:44 +0200 Message-ID: <20180731141146.10788-3-o.rempel@pengutronix.de> References: <20180731141146.10788-1-o.rempel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180731141146.10788-1-o.rempel@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Shawn Guo , Fabio Estevam , Rob Herring , Mark Rutland , "A.s. Dong" , Vladimir Zapolskiy , Jassi Brar Cc: Oleksij Rempel , dl-linux-imx , linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org Each MU has four pairs of rx/tx data register with four rx/tx interrupts which can also be used as a separate channel. Signed-off-by: Oleksij Rempel --- .../devicetree/bindings/mailbox/fsl,mu.txt | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index 90e4905dfc69..9efd3a9ade44 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -18,11 +18,33 @@ Messaging Unit Device Node: Required properties: ------------------- - compatible : should be "fsl,-mu", the supported chips include - imx8qxp, imx8qm. + imx6sx, imx7s, imx8qxp, imx8qm. + The "fsl,imx6sx-mu" compatible is seen as generic and should + be included together with SoC specific compatible. - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. -- #mbox-cells: Must be 0. Number of cells in a mailbox +- #mbox-cells: Must be 2. + <&phandle type channel> + phandle : Label name of controller + type : Channel type + channel : Channel number + + This MU support 4 type of unidirectional channels, each type + has 4 channels. A total of 16 channels. Following types are + supported: + 0 - TX channel with 32bit transmit register and IRQ transmit + acknowledgment support. + 1 - RX channel with 32bit receive register and IRQ support + 2 - TX doorbell channel. Without own register and no ACK support. + 3 - RX doorbell channel. + The doorbell channels should be used with shared memory and protocol + level acknowledgment if needed. + +Optional properties: +------------------- +- clocks : phandle to the input clock. +- fsl,mu-side-b : Should be set for side B MU. Examples: -------- @@ -30,5 +52,5 @@ lsio_mu0: mailbox@5d1b0000 { compatible = "fsl,imx8qxp-mu"; reg = <0x0 0x5d1b0000 0x0 0x10000>; interrupts = ; - #mbox-cells = <0>; + #mbox-cells = <2>; }; -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: o.rempel@pengutronix.de (Oleksij Rempel) Date: Tue, 31 Jul 2018 16:11:44 +0200 Subject: [PATCH v8 2/4] dt-bindings: mailbox: imx-mu: add generic MU channel support In-Reply-To: <20180731141146.10788-1-o.rempel@pengutronix.de> References: <20180731141146.10788-1-o.rempel@pengutronix.de> Message-ID: <20180731141146.10788-3-o.rempel@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Each MU has four pairs of rx/tx data register with four rx/tx interrupts which can also be used as a separate channel. Signed-off-by: Oleksij Rempel --- .../devicetree/bindings/mailbox/fsl,mu.txt | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index 90e4905dfc69..9efd3a9ade44 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -18,11 +18,33 @@ Messaging Unit Device Node: Required properties: ------------------- - compatible : should be "fsl,-mu", the supported chips include - imx8qxp, imx8qm. + imx6sx, imx7s, imx8qxp, imx8qm. + The "fsl,imx6sx-mu" compatible is seen as generic and should + be included together with SoC specific compatible. - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. -- #mbox-cells: Must be 0. Number of cells in a mailbox +- #mbox-cells: Must be 2. + <&phandle type channel> + phandle : Label name of controller + type : Channel type + channel : Channel number + + This MU support 4 type of unidirectional channels, each type + has 4 channels. A total of 16 channels. Following types are + supported: + 0 - TX channel with 32bit transmit register and IRQ transmit + acknowledgment support. + 1 - RX channel with 32bit receive register and IRQ support + 2 - TX doorbell channel. Without own register and no ACK support. + 3 - RX doorbell channel. + The doorbell channels should be used with shared memory and protocol + level acknowledgment if needed. + +Optional properties: +------------------- +- clocks : phandle to the input clock. +- fsl,mu-side-b : Should be set for side B MU. Examples: -------- @@ -30,5 +52,5 @@ lsio_mu0: mailbox at 5d1b0000 { compatible = "fsl,imx8qxp-mu"; reg = <0x0 0x5d1b0000 0x0 0x10000>; interrupts = ; - #mbox-cells = <0>; + #mbox-cells = <2>; }; -- 2.18.0