From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EF32C28CF6 for ; Wed, 1 Aug 2018 10:03:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 31D3D20844 for ; Wed, 1 Aug 2018 10:03:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 31D3D20844 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389235AbeHALsK (ORCPT ); Wed, 1 Aug 2018 07:48:10 -0400 Received: from shelob.surriel.com ([96.67.55.147]:55962 "EHLO shelob.surriel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389211AbeHALsK (ORCPT ); Wed, 1 Aug 2018 07:48:10 -0400 Received: from imladris.surriel.com ([96.67.55.152]) by shelob.surriel.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1fkny6-00010M-9X; Wed, 01 Aug 2018 06:02:58 -0400 From: Rik van Riel To: linux-kernel@vger.kernel.org Cc: kernel-team@fb.com, mingo@kernel.org, peterz@infradead.org, luto@kernel.org, x86@kernel.org, efault@gmx.de, dave.hansen@intel.com, Rik van Riel Subject: [PATCH 01/11] x86,tlb: clarify memory barrier in switch_mm_irqs_off Date: Wed, 1 Aug 2018 06:02:45 -0400 Message-Id: <20180801100255.4278-2-riel@surriel.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180801100255.4278-1-riel@surriel.com> References: <20180801100255.4278-1-riel@surriel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Clarify exactly what the memory barrier synchronizes with. Suggested-by: Peter Zijlstra Signed-off-by: Rik van Riel Reviewed-by: Andy Lutomirski --- arch/x86/mm/tlb.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 752dbf4e0e50..5321e02c4e09 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -263,8 +263,11 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, /* * Read the tlb_gen to check whether a flush is needed. * If the TLB is up to date, just use it. - * The barrier synchronizes with the tlb_gen increment in - * the TLB shootdown code. + * The TLB shootdown code first increments tlb_gen, and then + * sends IPIs to CPUs that have this CPU loaded and are not + * in lazy TLB mode. The barrier ensures we handle + * cpu_tlbstate.is_lazy before tlb_gen, keeping this code + * synchronized with the TLB flush code. */ smp_mb(); next_tlb_gen = atomic64_read(&next->context.tlb_gen); -- 2.14.4